Datasheet

2011-2012 Microchip Technology Inc. Preliminary DS61168E-page 105
PIC32MX1XX/2XX
REGISTER 9-2: DMASTAT: DMA STATUS REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0
U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
RDWR DMACH<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0
bit 3 RDWR: Read/Write Status bit
1 = Last DMA bus access was a read
0 = Last DMA bus access was a write
bit 2-0 DMACH<2:0>: DMA Channel bits
These bits contain the value of the most recent active DMA channel.
REGISTER 9-3: DMAADDR: DMA ADDRESS REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DMAADDR<31:24>
23:16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DMAADDR<23:16>
15:8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DMAADDR<15:8>
7:0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DMAADDR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 DMAADDR<31:0>: DMA Module Address bits
These bits contain the address of the most recent DMA access.