Datasheet

PIC32MX1XX/2XX
DS61168E-page 104 Preliminary  2011-2012 Microchip Technology Inc.
REGISTER 9-1: DMACON: DMA CONTROLLER CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0
ON
(1)
— — SUSPEND DMABUSY — — —
7:0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: DMA On bit
(1)
1 = DMA module is enabled
0 = DMA module is disabled
bit 14-13 Unimplemented: Read as ‘0’
bit 12 SUSPEND: DMA Suspend bit
1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus
0 = DMA operates normally
bit 11 DMABUSY: DMA Module Busy bit
1 = DMA module is active
0 = DMA module is disabled and not actively transferring data
bit 10-0 Unimplemented: Read as ‘0’
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.