PIC32MX1XX/2XX 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog Operating Conditions Timers/Output Compare/Input Capture • 2.3V to 3.6V, -40ºC to +105ºC, DC to 40 MHz • 2.3V to 3.
PIC32MX1XX/2XX Packages 2 5 3 N 2 Y 4/0 Y 10 Y 21 Y PIC32MX110F016C 36 16+3 4 24 5/5/5 2 2 5 3 N 2 Y 4/0 Y 12 Y 25 Y VTLA Y VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN Pins PIC32MX110F016D 44 16+3 4 32 5/5/5 2 2 5 3 N 2 Y 4/0 Y 13 Y I/O Pins 2 RTCC 5/5/5 CTMU 20 PMP 4 I2C™ 16+3 SPI/I2S 28 UART PIC32MX110F016B SOIC, SSOP, SPDIP, QFN Device JTAG USB On-The-Go (OTG) Analog Comparators External Interrupts(3) Timers(2)/Capture/Compare Remappab
PIC32MX1XX/2XX Packages 2 5 3 Y 2 Y 4/2 Y 9 Y 19 Y PIC32MX210F016C 36 16+3 4 23 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 12 Y 23 Y VTLA Y VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN Pins PIC32MX210F016D 44 16+3 4 31 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 13 Y I/O Pins 2 RTCC 5/5/5 CTMU 19 PMP 4 I2C™ 16+3 SPI/I2S 28 UART PIC32MX210F016B SOIC, SSOP, SPDIP, QFN Device JTAG USB On-The-Go (OTG) Analog Comparators External Interrupts(3) Timers(2)/Capture/Compare Remappabl
PIC32MX1XX/2XX Pin Diagrams 28-Pin SOIC, SPDIP, SSOP(1,2) = Pins are up to 5V tolerant MCLR PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 VSS OSC1/CLKI/RPA2/RA2 OSC2/CLKO/RPA3/PMA0/RA3 SOSCI/RPB4/RB4 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 VDD TMS/RPB5/USBID/RB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Note 1:
PIC32MX1XX/2XX Pin Diagrams (Continued) 28-Pin QFN(1,2,3) Note VREF-/CVREF-/AN1/RPA1/CTED2/RA1 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 MCLR AVDD AVSS AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 28 27 26 25 24 23 22 = Pins are up to 5V tolerant PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 1 21 AN11/RPB13/CTPLS/PMRD/RB13 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 2 20 AN12/PMD0/RB12 19 PGEC2/TMS/RPB11/PMD1/RB11 1: 2: 3: 11 12 13 14 PGEC3/RPB6/PMD6/RB6
PIC32MX1XX/2XX Pin Diagrams (Continued) 28-Pin QFN(1,2,3) Note 1: 2: 3: PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 MCLR AVDD AVSS AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 27 26 25 24 23 22 10 11 12 13 14 VDD TMS/RPB5/USBID/RB5 VBUS TDI/RPB7/CTED3/PMD5/INT0/RB7 TCK/RPB8/SCL1/CTED10/PMD4/RB8 OSC1/CLKI/RPA2/RA2 OSC2/CLKO/RPA3/PMA0/RA3 PIC32MX210F016B PIC32MX220F032B PIC32MX230F064B PIC32MX2
PIC32MX1XX/2XX Pin Diagrams (Continued) 36-Pin VTLA(1,2,3) PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 MCLR AVDD AVSS AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 AN11/RPB13/CTPLS/PMRD/RB13 = Pins are up to 5V tolerant 36 35 34 33 32 31 30 29 28 27 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 1 26 AN12/PMD0/RB12 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 2
PIC32MX1XX/2XX Pin Diagrams (Continued) 36-Pin VTLA(1,2,3) MCLR AVDD AVSS AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 AN11/RPB13/CTPLS/PMRD/RB13 35 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 36 PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 = Pins are up to 5V tolerant 34 33 32 31 30 29 28 27 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 1 26 VUSB3V3 AN5/C1I
PIC32MX1XX/2XX Pin Diagrams (Continued) 44-Pin QFN(1,2,3) RPB8/SCL1/CTED10/PMD4/RB8 RPB7/CTED3/PMD5/INT0/RB7 PGEC3/RPB6/PMD6/RB6 PGED3/RPB5/PMD7/RB5 VDD VSS RPC5/PMA3/RC5 RPC4/PMA4/RC4 RPC3/RC3 TDI/RPA9/PMA9/RA9 SOSCO/RPA4/T1CK/CTED9/RA4 44 43 42 41 40 39 38 37 36 35 34 = Pins are up to 5V tolerant RPB9/SDA1/CTED4/PMD3/RB9 1 33 SOSCI/RPB4/RB4 RPC6/PMA1/RC6 2 32 TDO/RPA8/PMA8/RA8 RPC7/PMA0/RC7 3 31 OSC2/CLKO/RPA3/RA3 RPC8/PMA5/RC8 4 30 OSC1/CLKI/RPA2/RA2 RPC9/CTED7/PMA
PIC32MX1XX/2XX Pin Diagrams (Continued) = Pins are up to 5V tolerant RPB8/SCL1/CTED10/PMD4/RB8 RPB7/CTED3/PMD5/INT0/RB7 VBUS RPB5/USBID/RB5 VDD VSS RPC5/PMA3/RC5 RPC4/PMA4/RC4 AN12/RPC3/RC3 TDI/RPA9/PMA9/RA9 SOSCO/RPA4/T1CK/CTED9/RA4 44 43 42 41 40 39 38 37 36 35 34 44-Pin QFN(1,2,3) RPB9/SDA1/CTED4/PMD3/RB9 1 33 SOSCI/RPB4/RB4 RPC6/PMA1/RC6 2 32 TDO/RPA8/PMA8/RA8 RPC7/PMA0/RC7 3 31 OSC2/CLKO/RPA3/RA3 RPC8/PMA5/RC8 4 30 OSC1/CLKI/RPA2/RA2 RPC9/CTED7/PMA6/RC9 5 29 V
PIC32MX1XX/2XX Pin Diagrams (Continued) 44-Pin TQFP(1,2,3) RPB8/SCL1/CTED10/PMD4/RB8 RPB7/CTED3/PMD5/INT0/RB7 PGEC3/RPB6/PMD6/RB6 PGED3/RPB5/PMD7/RB5 VDD VSS RPC5/PMA3/RC5 RPC4/PMA4/RC4 RPC3/RC3 TDI/RPA9/PMA9/RA9 SOSCO/RPA4/T1CK/CTED9/RA4 44 43 42 41 40 39 38 37 36 35 34 = Pins are up to 5V tolerant RPB9/SDA1/CTED4/PMD3/RB9 1 33 SOSCI/RPB4/RB4 RPC6/PMA1/RC6 2 32 TDO/RPA8/PMA8/RA8 RPC7/PMA0/RC7 3 31 OSC2/CLKO/RPA3/RA3 RPC8/PMA5/RC8 4 30 OSC1/CLKI/RPA2/RA2 RPC9/CTED7/PM
PIC32MX1XX/2XX Pin Diagrams (Continued) 44-Pin VTLA(1,2,3) RPB8/SCL1/CTED10/PMD4/RB8 RPB7/CTED3/PMD5/INT0/RB7 PGEC3/RPB6/PMD6/RB6 PGED3/RPB5/PMD7/RB5 VDD VSS RPC5/PMA3/RC5 RPC4/PMA4/RC4 RPC3/RC3 TDI/RPA9/PMA9/RA9 SOSCO/RPA4/T1CK/CTED9/RA4 SOSCI/RPB4/RB4 = Pins are up to 5V tolerant 44 43 42 41 40 39 38 37 36 35 34 33 RPB9/SDA1/CTED4/PMD3/RB9 1 32 TDO/RPA8/PMA8/RA8 RPC6/PMA1/RC6 2 31 OSC2/CLKO/RPA3/RA3 RPC7/PMA0/RC7 3 30 OSC1/CLKI/RPA2/RA2 RPC8/PMA5/RC8 4 29 VSS RPC9
PIC32MX1XX/2XX Pin Diagrams (Continued) = Pins are up to 5V tolerant RPB8/SCL1/CTED10/PMD4/RB8 RPB7/CTED3/PMD5/INT0/RB7 VBUS RPB5/USBID/RB5 VDD VSS RPC5/PMA3/RC5 RPC4/PMA4/RC4 AN12/RPC3/RC3 TDI/RPA9/PMA9/RA9 SOSCO/RPA4/T1CK/CTED9/RA4 44 43 42 41 40 39 38 37 36 35 34 44-Pin TQFP(1,2,3) RPB9/SDA1/CTED4/PMD3/RB9 1 33 SOSCI/RPB4/RB4 RPC6/PMA1/RC6 2 32 TDO/RPA8/PMA8/RA8 RPC7/PMA0/RC7 3 31 OSC2/CLKO/RPA3/RA3 RPC8/PMA5/RC8 4 30 OSC1/CLKI/RPA2/RA2 RPC9/CTED7/PMA6/RC9 5 29
PIC32MX1XX/2XX Pin Diagrams (Continued) = Pins are up to 5V tolerant 38 SOSCI/RPB4/RB4 39 SOSCO/RPA4/T1CK/CTED9/RA4 40 TDI/RPA9/PMA9/RA9 RPC5/PMA3/RC5 41 RPC4/PMA4/RC4 VSS 42 AN12/RPC3/RC3 VDD 43 VBUS RPB7/CTED3/PMD5/INT0/RB7 44 RPB5/USBID/RB5 RPB8/SCL1/CTED10/PMD4/RB8 44-Pin VTLA(1,2,3) 37 36 35 34 33 RPB9/SDA1/CTED4/PMD3/RB9 1 32 TDO/RPA8/PMA8/RA8 RPC6/PMA1/RC6 2 31 OSC2/CLKO/RPA3/RA3 RPC7/PMA0/RC7 3 30 OSC1/CLKI/RPA2/RA2 RPC8/PMA5/RC8 4 29 VSS RPC9/CTED7/PMA6/RC9
PIC32MX1XX/2XX Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 19 2.0 Guidelines for Getting Started with 32-bit MCUs........................................................................................................................ 27 3.0 CPU.........................................................................................................
PIC32MX1XX/2XX TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.
PIC32MX1XX/2XX Referenced Sources This device data sheet is based on the following individual chapters of the “PIC32 Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note: • • • • • • • • • • • • • • • • • • • • • • • • • • To access the documents listed below, browse to the documentation section of the Microchip web site (www.microchip.com). Section 1. “Introduction” (DS61127) Section 2.
PIC32MX1XX/2XX NOTES: DS61168E-page 18 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX 1.0 This document contains device-specific information for PIC32MX1XX/2XX devices. DEVICE OVERVIEW Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX1XX/2XX TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Number(1) 28-pin QFN 28-pin SSOP/ SPDIP/ SOIC 36-pin VTLA 44-pin QFN/ TQFP/ VTLA Pin Type Buffer Type AN0 27 2 33 19 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 28 1 2 3 4 — — — 23 22 21 3 4 5 6 7 — — — 26 25 24 20(2) 23(2) I Analog CLKI 6 9 20 21 22 23 24 25 26 27 15 14 11 10(2) 36(3) 30 Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog AN12 34 35 36 1 2 3 4 — 29 28 27 26(2) 11(3) 7 I I I I I
PIC32MX1XX/2XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name OC1 OC2 OC3 OC4 OC5 OCFA OCFB INT0 INT1 INT2 INT3 INT4 RA0 28-pin QFN 28-pin SSOP/ SPDIP/ SOIC 36-pin VTLA 44-pin QFN/ TQFP/ VTLA Pin Type Buffer Type PPS PPS PPS PPS PPS PPS PPS 13 PPS PPS PPS PPS 27 PPS PPS PPS PPS PPS PPS PPS 16 PPS PPS PPS PPS 2 PPS PPS PPS PPS PPS PPS PPS 17 PPS PPS PPS PPS 33 PPS PPS PPS PPS PPS PPS PPS 43 PPS PPS PPS PPS 19 O O O O O I I I I I I I — — — — — ST ST ST ST ST ST ST Descri
PIC32MX1XX/2XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 28-pin QFN 28-pin SSOP/ SPDIP/ SOIC 36-pin VTLA 44-pin QFN/ TQFP/ VTLA Pin Type Buffer Type RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 T1CK T2CK T3CK T4CK T5CK — — — — — — — — — — 9 PPS PPS PPS PPS — — — — — — — — — — 12 PPS PPS PPS PPS 3 4 — 11 — — — — — 20 10 PPS PPS PPS PPS 25 26 27 36 37 38 2 3 4 5 34 PPS PPS PPS PPS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST PORTC i
PIC32MX1XX/2XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 28-pin QFN 28-pin SSOP/ SPDIP/ SOIC 36-pin VTLA 44-pin QFN/ TQFP/ VTLA Pin Type Buffer Type SDA1 15 18 19 1 I/O ST SCL2 4 7 2 24 I/O ST SDA2 3 6 1 23 I/O ST 19(2) 11(3) 14 13 15 4 28 22(2) 14(3) 17 16 18 7 3 25(2) 15(3) 18 17 19 2 34 12 I ST 13 35 32 24 20 I O O I I ST — — ST Analog 27 22 4 2 25 7 33 28 2 19 14 24 I O Analog Analog Pin Name TMS TCK TDI TDO RTCC CVREFCVREF+ CVREFOUT C1INA
PIC32MX1XX/2XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 28-pin QFN 28-pin SSOP/ SPDIP/ SOIC 36-pin VTLA 44-pin QFN/ TQFP/ VTLA Pin Type Buffer Type PMA0 7 10 8 3 I/O TTL/ST PMA1 9 12 10 2 I/O TTL/ST 23 20(2) 1(3) 19(2) 2(3) 18(2) 3(3) 15 — — — — — — — — — 26 23(2) 4(3) 22(2) 5(3) 21(2) 6(3) 18 — — — — — — — — — 29 26(2) 35(3) 25(2) 36(3) 24(2) 1(3) 19 27 38 37 4 5 13 32 35 12 15 10(2) 21(3) 9(2) 22(3) 8(2) 23(3) 1 O O O O O O O O O O — — — — — — — — — — I/O TT
PIC32MX1XX/2XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 28-pin QFN 28-pin SSOP/ SPDIP/ SOIC 36-pin VTLA 44-pin QFN/ TQFP/ VTLA Pin Type Buffer Type USBID CTED1 CTED2 CTED3 CTED4 CTED5 CTED6 CTED7 CTED8 CTED9 CTED10 CTED11 CTED12 CTED13 CTPLS PGED1 11 27 28 13 15 22 23 — — 9 14 18 2 3 21 1 14 2 3 16 18 25 26 — — 12 17 21 5 6 24 4 15 33 34 17 19 28 29 20 — 10 18 24 36 1 27 35 41 19 20 43 1 14 15 5 13 34 44 8 22 23 11 21 I I I I I I I I I I I I I I O I/O ST ST ST ST ST ST ST ST
PIC32MX1XX/2XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name MCLR 28-pin QFN 28-pin SSOP/ SPDIP/ SOIC 36-pin VTLA 44-pin QFN/ TQFP/ VTLA Pin Type Buffer Type 26 1 32 18 I/P ST Description Master Clear (Reset) input. This pin is an active-low Reset to the device. 25 28 31 17 P — Positive supply for analog modules. This AVDD pin must be connected at all times.
PIC32MX1XX/2XX • All VDD and VSS pins (see 2.2 “Decoupling Capacitors”) • All AVDD and AVSS pins, even if the ADC module is not used (see 2.2 “Decoupling Capacitors”) • VCAP pin (see 2.3 “Capacitor on Internal Voltage Regulator (VCAP)”) • MCLR pin (see 2.4 “Master Clear (MCLR) Pin”) • PGECx/PGEDx pins, used for In-Circuit Serial Programming (ICSP™) and debugging purposes • (see 2.5 “ICSP Pins”) • OSC1 and OSC2 pins, when external oscillator source is used (see 2.
PIC32MX1XX/2XX 2.3 Capacitor on Internal Voltage Regulator (VCAP) 2.3.1 2.5 INTERNAL REGULATOR MODE A low-ESR (1 ohm) capacitor is required on the VCAP pin, which is used to stabilize the internal voltage regulator output. The VCAP pin must not be connected to VDD, and must have a CEFC capacitor, with at least a 6V rating, connected to ground. The type can be ceramic or tantalum. Refer to Section 29.0 “Electrical Characteristics” for additional information on CEFC specifications. 2.
PIC32MX1XX/2XX 2.7 External Oscillator Pins Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them.
PIC32MX1XX/2XX 2.9 Typical Application Connection Examples Examples of typical application connections are shown in Figure 2-4 and Figure 2-5.
PIC32MX1XX/2XX 3.0 CPU Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS61113) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). Resources for the MIPS32® M4K® Processor Core are available at: www.mips.com.
PIC32MX1XX/2XX 3.2 3.2.2 Architecture Overview The MIPS32® M4K® processor core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core: • • • • • • • • Execution Unit Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Fixed Mapping Translation (FMT) Dual Internal Bus interfaces Power Management MIPS16e Support Enhanced JTAG (EJTAG) Controller 3.2.
PIC32MX1XX/2XX The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be transferred to the General Purpose Register file. In addition to the HI/LO targeted operations, the MIPS32® architecture also defines a multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair.
PIC32MX1XX/2XX Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. Table 3-3 lists the exception types in order of priority. MIPS32® M4K® PROCESSOR CORE EXCEPTION TYPES TABLE 3-3: Exception Description Reset Assertion MCLR or a Power-on Reset (POR). DSS EJTAG debug single step. DINT EJTAG debug interrupt.
PIC32MX1XX/2XX 4.0 Note: MEMORY ORGANIZATION 4.1 This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source.For detailed information, refer to Section 3. “Memory Organization” (DS61115) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). PIC32MX1XX/2XX microcontrollers provide 4 GB of unified virtual memory address space.
PIC32MX1XX/2XX FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX11X/21X DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC00C00 0xBFC00BFF 0xBFC00BF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC00BEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD004000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD003FFF Program Flash(2) 0xBD000000 0xA0001000 Reserved 0xA0000FFF RAM(2) 0xA0000000 0x9FC00C00 0x9FC00BFF 0x9FC00BF0 0x1FC00C00 Device Configuration Registers Reserv
PIC32MX1XX/2XX FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX12X/22X DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC00C00 0xBFC00BFF 0xBFC00BF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC00BEF Boot Flash 0xBFC00000 0xBF900000 Reserved 0xBF8FFFFF Reserved 0xBD008000 Reserved KSEG1 SFRs 0xBF800000 0xBD007FFF Program Flash(2) 0xBD000000 0xA0002000 Reserved 0xA0001FFF RAM(2) 0xA0000000 0x9FC00C00 0x9FC00BFF 0x9FC00BF0 0x1FC00C00 Device Configuration Registers Reser
PIC32MX1XX/2XX FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX13X/23X DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC00C00 0xBFC00BFF 0xBFC00BF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC00BEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD010000 KSEG1 0xBF8FFFFF Reserved Reserved 0xBD00FFFF Program Flash(2) 0xBD000000 0xA0004000 Reserved 0xA0003FFF RAM(2) 0xA0000000 0x9FC00C00 0x9FC00BFF 0x9FC00BF0 0x1FC00C00 Device Configuration Registers Reserv
PIC32MX1XX/2XX FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX15X/25X DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC00C00 0xBFC00BFF 0xBFC00BF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC00BEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD020000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD01FFFF Program Flash(2) 0xBD000000 0xA0008000 Reserved 0xA0007FFF RAM(2) 0xA0000000 0x9FC00C00 0x9FC00BFF 0x9FC00BF0 0x1FC00C00 Device Configuration Registers Reserv
Special Function Registers Table 4-1 through Table 4-27 contain the Special Function Register (SFR) maps for the PIC32MX1XX/2XX devices.
Virtual Address (BF88_#) Register Name(1) 1000 INTCON INTERRUPT REGISTER MAP 31/15 30/14 29/13 31:16 — — 15:0 — — 31:16 1010 INTSTAT(3) 15:0 — — 1020 IPTMR 1030 IFS0 1040 IFS1 1060 IEC0 Preliminary 1070 IEC1 1090 IPC0 10A0 IPC1 10B0 IPC2 IPC3 10D0 IPC4 10E0 IPC5 10F0 IPC6 DS61168E-page 41 1100 IPC7 27/11 26/10 — — — — — MVEC — — — — — — — — — 25/9 24/8 23/7 22/6 21/5 — — — — — — — — — — INT4EP INT3EP — — — — — — — TPC<2:0> —
Virtual Address (BF88_#) Register Name(1) 1110 IPC8 INTERRUPT REGISTER MAP (CONTINUED) 1120 IPC9 1130 IPC10 31/15 30/14 29/13 28/12 27/11 31:16 — — — PMPIP<2:0> 15:0 — — — I2C1IP<2:0> 31:16 — — — 15:0 — — 31:16 — 15:0 — 26/10 25/9 24/8 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits 23/7 22/6 21/5 PMPIS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000 I2C1IS<1:0> — — — U1IP<2:0> U1IS<1:0> 0000 CTMUIP<2:0> CTMUIS<1:0> — — — I2C2IP<2:0> I2C2IS<1:0> 0
Virtual Address (BF80_#) TMR1 0620 PR1 PR2 Preliminary PR3 27/11 26/10 25/9 24/8 — — ON — SIDL — — — — TWDIS TWIP — — 31:16 — — — — — — — 15:0 20/4 19/3 — — — — — — — TGATE — TCKPS<1:0> — — — — — — — — — — — — — — — — — — — 31:16 — — — — — — — — — 15:0 ON — SIDL — — — — — TGATE 31:16 — — — — — — — — — — 16/0 — — — 0000 TSYNC TCS — 0000 — — — 0000 — — — — 0000 — — — — 0000 0000 FFFF T32 — T
Virtual Address (BF80_#) IC1BUF 2200 IC2CON 2210 (1) IC2BUF 31/15 30/14 31:16 — 15:0 ON IC3BUF Preliminary 2600 IC4CON 2610 (1) IC4BUF IC5BUF 27/11 26/10 25/9 — — — — — — — SIDL — — — FEDGE 24/8 23/7 22/6 21/5 — — — — C32 ICTMR 31:16 — — — — — — — — — 15:0 ON — SIDL — — — FEDGE C32 ICTMR 31:16 — — — — — — — — — ON — SIDL — — — FEDGE C32 ICTMR 31:16 18/2 — — — ICOV ICBNE 17/1 16/0 — — ICM<2:0> 31:16 — — — — — —
Virtual Address (BF80_#) 3000 OC1CON 3010 3020 OC1R OC1RS 3200 OC2CON 3210 3220 OC2R OC2RS Preliminary 3400 OC3CON 3410 3420 OC3R 3610 OC4R 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 31:16 — 15:0 ON — — — — — — — — — — — SIDL — — — — — — — OC32 31:16 15:0 31:16 15:0 OC5R OC5RS 20/4 19/3 18/2 — — — OCFLT OCTSEL xxxx — — — — — — — — — 15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL xxxx — — — — — — — — — 15:0 ON — SIDL —
Virtual Address (BF80_#) 5010 I2C1STAT I2C1ADD 5030 I2C1MSK 5040 I2C1BRG 5050 Preliminary 5060 I2C1TRN I2C1RCV 5100 I2C2CON 5110 I2C2STAT 5120 I2C2ADD 5130 I2C2MSK 5140 I2C2BRG 2011-2012 Microchip Technology Inc.
Virtual Address (BF80_#) U1STA(1) 6020 U1TXREG 6030 U1RXREG 6040 U1BRG(1) 6200 U2MODE Preliminary 6210 (1) U2STA(1) 6220 U2TXREG 6230 U2RXREG 6240 U2BRG(1) 31/15 30/14 31:16 — — — 15:0 ON — SIDL — — 31:16 15:0 UTXISEL<1:0> 29/13 28/12 27/11 26/10 25/9 24/8 — — — — — IREN RTSMD — UEN<1:0> — — — — — ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT 31:16 — — — — — — — — 15:0 — — — — — — — TX8 31:16 — — — — — — — — 15:0 — — — — — —
5800 SPI1CON 5810 SPI1STAT 5820 SPI1BUF 5830 SPI1BRG 5840 SPI1CON2 5A00 SPI2CON Preliminary 5A10 SPI2STAT 5A20 SPI2BUF 5A30 SPI2BRG 5A40 SPI2CON2 31/15 30/14 29/13 31:16 FRMEN 15:0 ON FRMSYNC FRMPOL — SIDL 31:16 — — — 15:0 — — — 28/12 27/11 MSSEN FRMSYPW DISSDO MODE32 26/10 25/9 24/8 FRMCNT<2:0> MODE16 SMP 23/7 SPIBUSY — — 20/4 — — — SSEN CKP MSTEN DISSDI — — — SRMT SPIROV SPIRBE RXBUFELM<4:0> FRMERR 21/5 MCLKSEL CKE SPITUR 31:16 22/6 19/3 18/2 17/1
ADC REGISTER MAP Register Name 9000 AD1CON1(1) 9010 AD1CON2(1) 9020 AD1CON3(1) 9040 AD1CHS(1) (1) 9050 AD1CSSL 9070 ADC1BUF0 9080 ADC1BUF1 Preliminary 9090 ADC1BUF2 90A0 ADC1BUF3 90B0 ADC1BUF4 90C0 ADC1BUF5 90D0 ADC1BUF6 90F0 ADC1BUF8 9100 ADC1BUF9 9110 ADC1BUFA 9120 ADC1BUFB 30/14 29/13 31:16 — — — — SIDL 15:0 ON 31:16 — — — 15:0 VCFG<2:0> 31:16 — — — — — 15:0 ADRC 31:16 CH0NB — — — — — 15:0 31:16 — — — 15:0 CSSL15 CSSL14 CSSL13 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31
Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 ADC Result Word E (ADC1BUFE<31:0>) 15:0 31:16 9160 ADC1BUFF ADC Result Word F (ADC1BUFF<31:0>) 15:0 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.
DMA GLOBAL REGISTER MAP 3000 DMACON 3010 DMASTAT 3020 DMAADDR 31/15 30/14 29/13 31:16 — — — 15:0 ON — — 31:16 — — — — 15:0 — — — — All Resets Bit Range Bits Register Name(1) Virtual Address (BF88_#) 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — 0000 — — — — — — — — — — — 0000 — — — — — — — — — — — — 0000 — — — — — — — — RDWR SUSPEND DMABUSY 31:16 DMACH<2:0>(2) 0000 0000
Virtual Address (BF88_#) 3070 DCH0ECON DCH0INT 3090 DCH0SSA 30A0 DCH0DSA 30B0 DCH0SSIZ Preliminary 30C0 DCH0DSIZ 30D0 DCH0SPTR 30E0 DCH0DPTR 30F0 DCH0CSIZ 3100 DCH0CPTR 3110 DCH0DAT 2011-2012 Microchip Technology Inc.
Virtual Address (BF88_#) 3170 DCH1SSIZ 3180 DCH1DSIZ 3190 DCH1SPTR 31A0 DCH1DPTR 31B0 DCH1CSIZ 31C0 DCH1CPTR Preliminary 31D0 DCH1DAT 31E0 DCH2CON 31F0 DCH2ECON 3200 DMA CHANNELS 0-3 REGISTER MAP (CONTINUED) DCH2INT 3210 DCH2SSA 3230 DCH2SSIZ 3240 DCH2DSIZ 3250 DCH2SPTR DS61168E-page 53 3260 DCH2DPTR 3270 DCH2CSIZ 31:16 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — 20/4 19/3 18/2 17/1 16/0 — — — —
Virtual Address (BF88_#) 3290 DCH2DAT 32A0 DCH3CON 32B0 DCH3ECON DCH3INT 32D0 DCH3SSA Preliminary 32E0 DCH3DSA 32F0 DCH3SSIZ 3300 DCH3DSIZ 3310 DCH3SPTR 3320 DCH3DPTR 3330 DCH3CSIZ 2011-2012 Microchip Technology Inc.
Virtual Address (BF80_#) COMPARATOR REGISTER MAP A000 CM1CON A010 CM2CON A020 CM3CON A060 CMSTAT 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 — 31:16 — — — — — — — — 15:0 ON COE CPOL — — — — COUT 31:16 — — — — — — — — 15:0 ON COE CPOL — — — — COUT 31:16 — — — — — — — — 15:0 ON COE CPOL — — — — COUT 31:16 — — — — — — — 15:0 — — SIDL — — — — 20/4 19/3 18/2 17/1 16/0 — — — — — — — EVPOL<1:0> — CRE
Virtual Address (BF80_#) Register Name F400 NVMCON(1) NVMKEY NVMADDR(1) F430 NVMDATA F440 NVMSRCADDR 31/15 30/14 29/13 31:16 — — — 15:0 WR WREN WRERR 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 — — — — — — — — — — — — — — — — — LVDERR LVDSTAT 18/2 17/1 16/0 — — — NVMOP<3:0> All Resets Bit Range Bits F410 F420 FLASH CONTROLLER REGISTER MAP 0000 0000 NVMKEY<31:0> 0000 NVMADDR<31:0> 0000 NVMDATA
Virtual Address (BF80_#) F000 OSCCON F010 OSCTUN F020 REFOCON F030 REFOTRIM 0000 WDTCON F600 RCON Preliminary F610 RSWRST F200 CFGCON F230 SYSTEM CONTROL REGISTER MAP SYSKEY(3) PMD1 F250 PMD2 PMD3 F260 PMD4 F270 F280 PMD5 F290 PMD6 30/14 29/13 28/12 27/11 26/10 31:16 — — 15:0 — 31:16 — — — — — — — — — — 15:0 — — — — — — — — — — 31:16 — 15:0 ON PLLODIV<2:0> COSC<2:0> 25/9 24/8 FRCDIV<2:0> — 23/7 — 22/6 20/4 SOSCRDY PBDIVRDY CLKLOCK ULOCK(4) NOSC<2:
2FF0 DEVCFG3 2FF4 DEVCFG2 2FF8 DEVCFG1 2FFC DEVCFG0 30/14 29/13 28/12 31:16 FVBUSONIO FUSBIDIO IOL1WAY PMDL1WAY 27/11 26/10 25/9 — — — 15:0 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — USERID<15:0> 31:16 — — — — — 15:0 UPLLEN(1) — — — — 31:16 — — — — — — 15:0 FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC 31:16 — — — — — 15:0 CP — — — — UPLLIDIV<2:0>(1) PWP<5:0> — — — — FPLLMUL<2:0> FWDTWINSZ<1:0> FWDTEN WINDIS POSCMOD<1:0> — F
Virtual Address (BF88_#) 6000 ANSELA 6010 6020 TRISA PORTA 6030 LATA 6040 ODCA Preliminary 6050 CNPUA 6060 CNPDA 6070 CNCONA 6080 PORTA REGISTER MAP CNENA 6090 CNSTATA 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — — — ANSA1 ANSA0 0003 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — TRISA10(2) TRISA9(2) TRIS
Virtual Address (BF88_#) 6110 TRISB 6120 PORTB 6130 LATB 6140 ODCB Preliminary 6150 CNPUB 6160 CNPDB 6170 CNCONB CNENB 6190 CNSTATB 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name Bits 6100 ANSELB 6180 PORTB REGISTER MAP 31:16 — — — — — — — — — — — — — — — — 15:0 ANSB15 ANSB14 ANSB13 ANSB12(2) — — — — — — — — ANSB3 ANSB2 ANSB1 ANSB0 E00F 31:16 — — — — — — —
Virtual Address (BF88_#) 6200 ANSELC 6210 6220 TRISC PORTC 6230 LATC 6240 ODCC Preliminary 6250 CNPUC 6260 CNPDC 6270 CNCONC 6280 PORTC REGISTER MAP CNENC 6290 CNSTATC 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits Register Name(1,2) 2011-2012 Microchip Technology Inc.
Register Name 2011-2012 Microchip Technology Inc.
Register Name Preliminary Virtual Address (BF80_#) FA54 U1CTSR FA58 U2RXR FA5C U2CTSR FA84 SDI1R FA88 SS1R FA90 SDI2R FA94 SS2R PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED) FAB8 REFCLKIR 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 31:16 — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — —
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP 2011-2012 Microchip Technology Inc.
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED) Preliminary FB54 RPB10R FB58 RPB11R FB60 RPB13R FB64 RPB14R FB68 RPB15R FB6C RPC0R(3) FB70 RPC1R(3) FB74 RPC2R(1) FB78 RPC3R(3) FB7C RPC4R(1) FB80 RPC5R(1) FB84 RPC6R(1) FB88 RPC7R(1) FB8C RPC8R(1) FB90 RPC9R(3) Legend: Note 1: 2: 3: 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — —
Virtual Address (BF80_#) Register Name(1) 7000 PMCON PARALLEL MASTER PORT REGISTER MAP 7010 PMMODE 7020 PMADDR 7030 PMDOUT 7040 PMDIN Preliminary 7050 PMAEN 7060 PMSTAT 31/15 30/14 29/13 31:16 — — — 15:0 ON — SIDL 31:16 — — — 15:0 BUSY 31:16 — — — — — 15:0 — CS1 — — — IRQM<1:0> 28/12 27/11 — — ADRMUX<1:0> — — INCM<1:0> 26/10 25/9 24/8 23/7 22/6 — — — — — PMPTTL PTWREN PTRDEN — — — MODE<1:0> WAITB<1:0> — — — 15:0 31:16 15:0 — — — — — 15:
Virtual Address (BF80_#) Register Name(1) 0200 RTCCON RTCC REGISTER MAP 0210 RTCALRM 0220 RTCTIME 0230 RTCDATE 0240 ALRMTIME 0250 ALRMDATE 31:16 — 15:0 ON 31:16 — 15:0 ALRMEN 29/13 28/12 27/11 26/10 25/9 24/8 — — — — — — SIDL — — — — — — — — — — — — CHIME PIV ALRMSYNC 15:0 SEC10<3:0> SEC01<3:0> 31:16 YEAR10<3:0> YEAR01<3:0> 15:0 DAY10<3:0> DAY01<3:0> 31:16 HR10<3:0> HR01<3:0> 15:0 SEC10<3:0> SEC01<3:0> — — — 20/4 — DAY10<3:0> — 19/3 18/2 17/1
Virtual Address (BF88_#) Register Name(1) 5040 U1OTGIR(2) 5050 U1OTGIE 5080 U1OTGCON U1PWRC U1IR(2) 5200 Preliminary 5210 5220 U1IE U1EIR(2) 5230 5240 U1EIE U1STAT 2011-2012 Microchip Technology Inc.
Virtual Address (BF88_#) Register Name(1) 5280 U1FRML(3) 5290 (3) U1FRMH U1TOK 52B0 52D0 Preliminary 52E0 U1SOF U1BDTP2 U1BDTP3 U1CNFG1 5300 U1EP0 5310 U1EP1 5320 U1EP2 5330 U1EP3 U1EP4 5350 U1EP5 5360 U1EP6 5370 U1EP7 DS61168E-page 69 5380 U1EP8 Legend: Note 1: 2: 3: 4: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — 31:16 — — —
Virtual Address (BF88_#) Register Name(1) 5390 U1EP9 USB REGISTER MAP (CONTINUED) 53A0 U1EP10 53B0 U1EP11 53C0 U1EP12 53D0 U1EP13 53E0 U1EP14 Preliminary 53F0 U1EP15 Legend: Note 1: 2: 3: 4: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — — — — — — 15:0 — — — — — — — — — — — 31:16 — — — — — — — — — — — 15:0 — — — — — — — — — — — 31:16 — — — — — — — — — — — 15:0 — — — — — — — — —
PIC32MX1XX/2XX 4.3 Control Registers Register 4-1 through Register 4-8 are used for setting the RAM and Flash memory partitions for data and code.
PIC32MX1XX/2XX REGISTER 4-2: Bit Range 31:24 23:16 15:8 7:0 BMXDKPBA: DATA RAM KERNEL PROGRAM BASE ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXDKPBA<15:8> R-0 R-0 BMXDKPBA<7:0> Legend: R = Readable
PIC32MX1XX/2XX REGISTER 4-3: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 BMXDUDBA<15:8> R-0 7:0 BMXDUDBA: DATA RAM USER DATA BASE ADDRESS REGISTER R-0 R-0 R-0 R-0 BMXDUDBA<7:0> Legend: R = Readable bi
PIC32MX1XX/2XX REGISTER 4-4: Bit Range 31:24 23:16 15:8 7:0 BMXDUPBA: DATA RAM USER PROGRAM BASE ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXDUPBA<15:8> R-0 R-0 BMXDUPBA<7:0> Legend: R = Readable b
PIC32MX1XX/2XX REGISTER 4-5: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R R R Bit Bit 28/20/12/4 27/19/11/3 R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R R R R R R R R R R R BMXDRMSZ<31:24> R R R R R BMXDRMSZ<23:16> R R R R R BMXDRMSZ<15:8> R 7:0 BMXDRMSZ: DATA RAM SIZE REGISTER R R R R BMXDRMSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clea
PIC32MX1XX/2XX REGISTER 4-7: Bit Range 31:24 23:16 15:8 7:0 BMXPFMSZ: PROGRAM FLASH (PFM) SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R R R R R R Bit Bit 28/20/12/4 27/19/11/3 R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R R R R R R R R R R R BMXPFMSZ<31:24> R R BMXPFMSZ<23:16> R R R R R R R R BMXPFMSZ<15:8> R R BMXPFMSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = B
PIC32MX1XX/2XX 5.0 FLASH PROGRAM MEMORY Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. “Flash Program Memory” (DS61121) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices.
PIC32MX1XX/2XX REGISTER 5-1: Bit Range NVMCON: PROGRAMMING CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 23:16 15:8 7:0 — — — — — — — — R/W-0 R/W-0 R-0 R-0 R-0 U-0 U-0 U-0 WR WREN U-0 U-0 U-0 U-0 — — — — Legend: R = Readable bit -n = Value at POR WRERR(1) LVDERR(1) LVDSTAT(1
PIC32MX1XX/2XX REGISTER 5-2: Bit Range 31:24 23:16 15:8 7:0 NVMKEY: PROGRAMMING UNLOCK REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 W-0 W-0 W-0 Bit Bit 28/20/12/4 27/19/11/3 W-0 W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<31:24> W-0 W-0 W-0 W-0 W-0 NVMKEY<23:16> W-0 W-0 W-0 W-0 W-0 NVMKEY<15:8> W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘
PIC32MX1XX/2XX REGISTER 5-4: Bit Range 31:24 23:16 15:8 7:0 NVMDATA: FLASH PROGRAM DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<23:16> R/W-0 NVMDATA<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<7:0> Legend:
PIC32MX1XX/2XX 6.0 RESETS Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. “Resets” (DS61118) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.
PIC32MX1XX/2XX REGISTER 6-1: Bit Range 31:24 23:16 15:8 7:0 RCON: RESET CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0 — — — — — — CMR VREGS R/W-0, HS R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS EXTR SWR — WDTO SLEEP IDLE
PIC32MX1XX/2XX REGISTER 6-2: Bit Range 31:24 23:16 15:8 7:0 RSWRST: SOFTWARE RESET REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 — — U-0 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 — U-0 U-0 U-0 U-0 U-0 U-0 W-0, HC — — — — — — — SWRST(1) Legend: HC = Cleared by h
PIC32MX1XX/2XX NOTES: DS61168E-page 84 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX 7.0 The PIC32MX1XX/2XX interrupt module includes the following features: INTERRUPT CONTROLLER Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Interrupt Controller” (DS61108) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX1XX/2XX TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION Interrupt Source(1) IRQ Vector # # Interrupt Bit Location Flag Enable Priority Sub-priority Persistent Interrupt IPC0<4:2> IPC0<1:0> No Highest Natural Order Priority CT – Core Timer Interrupt 0 0 IFS0<0> IEC0<0> CS0 – Core Software Interrupt 0 1 1 IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8> No CS1 – Core Software Interrupt 1 2 2 IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16> No INT0 – External Interrupt 3 3 IFS0<3> IEC
PIC32MX1XX/2XX TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED) Interrupt Source(1) IRQ Vector # # Interrupt Bit Location Flag Enable Priority Sub-priority Persistent Interrupt U1E – UART1 Fault 39 32 IFS1<7> IEC1<7> IPC8<4:2> IPC8<1:0> Yes U1RX – UART1 Receive Done 40 32 IFS1<8> IEC1<8> IPC8<4:2> IPC8<1:0> Yes U1TX – UART1 Transfer Done 41 32 IFS1<9> IEC1<9> IPC8<4:2> IPC8<1:0> Yes I2C1B – I2C1 Bus Collision Event 42 33 IFS1<10> IEC1<10> IPC8<12:10> IPC8<9:
PIC32MX1XX/2XX REGISTER 7-1: Bit Range 31:24 23:16 15:8 7:0 INTCON: INTERRUPT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 R/W-0 — — — — U-0 U-0 SS0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — — — MVEC — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP I
PIC32MX1XX/2XX REGISTER 7-2: Bit Range 31:24 23:16 15:8 7:0 INTSTAT: INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — U-0 U-0 R/W-0 R/W-0 R/W-0 — — Legend: R = Readable bit -n = Value at POR Bit Bit 28/20/12/4 27/19/11/3 SRIPL<2:0>(1) R/W-0
PIC32MX1XX/2XX REGISTER 7-4: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 IFSx: INTERRUPT FLAG STATUS REGISTER Bit 30/22/14/6 Note: 31:24 23:16 15:8 7:0 Note: Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS30 IFS29 IFS28 IFS27 IFS26 IFS25 IFS24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS23 IFS22 IFS21 IFS20 IFS19 IFS18 IFS17 IFS16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS15 IFS14 IFS13 IFS12 IFS11 IFS10 IFS09 I
PIC32MX1XX/2XX REGISTER 7-6: Bit Range IPCx: INTERRUPT PRIORITY CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — 31:24 23:16 15:8 7:0 Legend: R = Readable bit -n = Value at POR Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 IP03<2:0> R/W-0 R/W-0 IS03<1:0> R/W-0 IP02<2:0> R/W-0 R/W-0 R/W-0 IP00<2:0> W = Writable bit ‘1’ = Bi
PIC32MX1XX/2XX REGISTER 7-6: bit 9-8 bit 7-5 bit 4-2 IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED) IS01<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as ‘0’ IP00<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 • • • bit 1-0 Note: 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled IS00<1:0>: Interrupt Subpriority
PIC32MX1XX/2XX 8.0 OSCILLATOR CONFIGURATION Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 6. “Oscillator Configuration” (DS61112) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX1XX/2XX FIGURE 8-1: OSCILLATOR DIAGRAM USB PLL(5) USB Clock (48 MHz) div x UFIN PLL x24 div 2 UFRCEN UPLLEN UFIN 4 MHz UPLLIDIV<2:0> ROTRIM<8:0> (M) REFCLKI POSC FRC LPRC SOSC PBCLK SYSCLK 4 MHz FIN 5 MHz FIN div x PLL REFCLKO M 2 N + --------512 To SPI RODIV<4:0> (N) ROSEL<3:0> FPLLIDIV<2:0> COSC<2:0> OE PLLMULT<2:0> div y XTPLL, HSPLL, ECPLL, FRCPLL PLLODIV<2:0> Primary Oscillator (POSC) OSC1 C1(3) RF(2) XTAL RP(1) RS(1) C2(3) OSC2(4) POSC (XT, HS, EC) To In
PIC32MX1XX/2XX REGISTER 8-1: Bit Range 31:24 23:16 15:8 7:0 OSCCON: OSCILLATOR CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 R/W-y — — U-0 R-0 — U-0 R/W-y — Bit 26/18/10/2 R/W-y R/W-0 PLLODIV<2:0> R-1 SOSCRDY PBDIVRDY R-0 Bit Bit 28/20/12/4 27/19/11/3 R-0 R/W-y Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-1 FRCDIV<2:0> R/W-y R/W-y PBDIV<1:0> R-0 R/W-y PLLMULT<2:0> U-0 COSC<2:0> R/W-y R/W-y — R/W-y R/W-y NOSC<2:0> R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0
PIC32MX1XX/2XX REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER bit 18-16 PLLMULT<2:0>: Phase-Locked Loop (PLL) Multiplier bits 111 = Clock is multiplied by 24 110 = Clock is multiplied by 21 101 = Clock is multiplied by 20 100 = Clock is multiplied by 19 011 = Clock is multiplied by 18 010 = Clock is multiplied by 17 001 = Clock is multiplied by 16 000 = Clock is multiplied by 15 bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits 111 = Internal Fast RC (FRC) Oscilla
PIC32MX1XX/2XX REGISTER 8-1: bit 3 bit 2 bit 1 bit 0 Note 1: Note: OSCCON: OSCILLATOR CONTROL REGISTER CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected UFRCEN: USB FRC Clock Enable bit(1) 1 = Enable FRC as the clock source for the USB clock source 0 = Use the Primary Oscillator or USB PLL as the USB clock source SOSCEN: Secondary Oscillator (SOSC) Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator OSWEN: Oscillator Switch E
PIC32MX1XX/2XX REGISTER 8-2: Bit Range 31:24 23:16 15:8 7:0 OSCTUN: FRC TUNING REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — R/W-0 (1) TUN<5:0> Legend: R = Readable bit W = Wr
PIC32MX1XX/2XX REGISTER 8-3: Bit Range 31:24 23:16 15:8 7:0 REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — R/W-0 RODIV<14:8>(3) R/W-0 R/W-0 R/W-0 R/W-0 RODIV<7:0> (3) R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R-0, HS, HC ON — SIDL OE RSLP(2) — DIVSWEN ACTIVE U-0 U-0 U-0 U-0 R/W-0
PIC32MX1XX/2XX REGISTER 8-3: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER bit 3-0 ROSEL<3:0>: Reference Clock Source Select bits(1) 1111 = Reserved; do not use • • • 1001 = Reserved; do not use 1000 = REFCLKI 0111 = System PLL output 0110 = USB PLL output 0101 = SOSC 0100 = LPRC 0011 = FRC 0010 = POSC 0001 = PBCLK 0000 = SYSCLK Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may result.
PIC32MX1XX/2XX REGISTER 8-4: Bit Range 31:24 23:16 15:8 7:0 REFOTRIM: REFERENCE OSCILLATOR TRIM REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 ROTRIM<8:1> R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 ROTRIM<0> — — — — — — — U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — Legend: R
PIC32MX1XX/2XX NOTES: DS61168E-page 102 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX 9.0 DIRECT MEMORY ACCESS (DMA) CONTROLLER Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. “Direct Memory Access (DMA) Controller” (DS61117) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX1XX/2XX REGISTER 9-1: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 DMACON: DMA CONTROLLER CONTROL REGISTER Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 U-0 U-0 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 (1) U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 — — SUSPEND DMABUSY — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — ON Legend: R
PIC32MX1XX/2XX REGISTER 9-2: Bit Range 31:24 23:16 15:8 7:0 DMASTAT: DMA STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — RDWR DMACH<2:0> Legend: R = Readable bit W = Wri
PIC32MX1XX/2XX REGISTER 9-4: Bit Range 31:24 23:16 15:8 7:0 DCRCCON: DMA CRC CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 R/W-0 R/W-0 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 R/W-0 R/W-0 (1) — — WBO — — BITO U-0 U-0 U-0 BYTO<1:0> U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — R/W-0 R/W-0 R/W-0 U-0 U-0 PLEN<4:0> CRCEN CRCAPP(1) CRCTYP
PIC32MX1XX/2XX REGISTER 9-4: DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED) bit 6 CRCAPP: CRC Append Mode bit(1) 1 = The DMA transfers data from the source into the CRC but NOT to the destination.
PIC32MX1XX/2XX REGISTER 9-5: Bit Range 31:24 23:16 15:8 7:0 DCRCDATA: DMA CRC DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<7:0> Legend
PIC32MX1XX/2XX REGISTER 9-7: Bit Range 31:24 23:16 15:8 7:0 DCHxCON: DMA CHANNEL ‘x’ CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 CHBUSY — — — — — — CHCHNS(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 CHEN(2) CHAED CHCHN
PIC32MX1XX/2XX REGISTER 9-8: Bit Range 31:24 23:16 DCHxECON: DMA CHANNEL ‘x’ EVENT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 (1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CHAIRQ<7:0> 15:8 R/W-1 CHSIRQ<7:0>(1) 7:0 S-0 S-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CFORCE CABORT PA
PIC32MX1XX/2XX REGISTER 9-9: Bit Range 31:24 23:16 15:8 7:0 DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W
PIC32MX1XX/2XX REGISTER 9-9: DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER (CONTINUED) bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit 1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2) 0 = No interrupt is pending bit 3 CHBCIF: Channel Block Transfer Complete Interrupt Flag bit 1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a pattern match event occurs 0 = No interrupt is pending bit 2 CHCC
PIC32MX1XX/2XX REGISTER 9-10: Bit Range DCHxSSA: DMA CHANNEL ‘x’ SOURCE START ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 R/W-0 R/W-0 31:24 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 R/W-0 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<31:24> R/W-0 23:16 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<23:16> R/W-0 15:8 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<15:8> R/W-0 7:0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<
PIC32MX1XX/2XX REGISTER 9-12: Bit Range 31:24 23:16 15:8 DCHxSSIZ: DMA CHANNEL ‘x’ SOURCE SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSIZ<15:8> R/W-0 7:0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSIZ<7:0> Legend: R
PIC32MX1XX/2XX REGISTER 9-14: Bit Range 31:24 23:16 15:8 DCHxSPTR: DMA CHANNEL ‘x’ SOURCE POINTER REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHSPTR<15:8> 7:0 R-0 R-0 CHSPTR<7:0> Legend: R = Readable bit -n = Value a
PIC32MX1XX/2XX REGISTER 9-16: Bit Range 31:24 23:16 15:8 DCHxCSIZ: DMA CHANNEL ‘x’ CELL-SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHCSIZ<15:8> R/W-0 7:0 R/W-0 R/W-0 R/W-0 R/W-0 CHCSIZ<7:0> Legend: R =
PIC32MX1XX/2XX REGISTER 9-18: Bit Range 31:24 23:16 15:8 7:0 DCHxDAT: DMA CHANNEL ‘x’ PATTERN DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHPDAT<7:0> Legend: R = Rea
PIC32MX1XX/2XX NOTES: DS61168E-page 118 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX 10.0 USB ON-THE-GO (OTG) Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 27. “USB OnThe-Go (OTG)” (DS61126) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices.
PIC32MX1XX/2XX FIGURE 10-1: PIC32MX1XX/2XX FAMILY USB INTERFACE DIAGRAM FRC Oscillator 8 MHz Typical TUN<5:0>(3) Primary Oscillator (POSC) Div x UFIN(4) PLL Div 2 UFRCEN(2) OSC1 UPLLEN(5) UPLLIDIV(5) OSC2 USB Module USB Voltage Comparators SRP Charge Bus SRP Discharge 48 MHz USB Clock(6) Full Speed Pull-up D+(1) Registers and Control Interface Host Pull-down SIE Transceiver Low Speed Pull-up D-(1) DMA System RAM Host Pull-down ID Pull-up ID(1) VBUSON(1) VUSB3V3 Note 1: 2: 3: 4: 5: 6
PIC32MX1XX/2XX REGISTER 10-1: Bit Range 31:24 23:16 15:8 7:0 U1OTGIR: USB OTG INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS U-0 R/WC-0, HS
PIC32MX1XX/2XX REGISTER 10-2: Bit Range 31:24 23:16 15:8 7:0 U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 IDIE T1MSECIE LSTATEIE ACTVIE
PIC32MX1XX/2XX REGISTER 10-3: Bit Range 31:24 23:16 15:8 7:0 U1OTGSTAT: USB OTG STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 U-0 R-0 U-0 R-0 R-0 U-0 R-0 ID — LSTATE — SESVD SESEND — VBUSVD Legend: R =
PIC32MX1XX/2XX REGISTER 10-4: Bit Range 31:24 23:16 15:8 7:0 U1OTGCON: USB OTG CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 DPPULUP DMPULUP DPPULDWN DMPULDWN R/W-0 R/W-0 R/W-0 R/W-0 VBUSO
PIC32MX1XX/2XX REGISTER 10-5: Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U-0 U1PWRC: USB POWER CONTROL REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UACTPND — — USLPGRD USBBUSY(1) — USUSPEND USB
PIC32MX1XX/2XX REGISTER 10-6: Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U1IR: USB INTERRUPT REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R-0 IDLEIF TRNIF(3) SOFIF UERR
PIC32MX1XX/2XX REGISTER 10-7: Bit Range 31:24 23:16 15:8 7:0 U1IE: USB INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STALLIE ATTACHIE RESUMEIE IDLEIE T
PIC32MX1XX/2XX REGISTER 10-8: Bit Range 31:24 23:16 15:8 7:0 U1EIR: USB ERROR INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/W
PIC32MX1XX/2XX REGISTER 10-8: U1EIR: USB ERROR INTERRUPT STATUS REGISTER (CONTINUED) bit 1 CRC5EF: CRC5 Host Error Flag bit(4) 1 = Token packet rejected due to CRC5 error 0 = Token packet accepted EOFEF: EOF Error Flag bit(3,5) 1 = EOF error condition detected 0 = No EOF error condition bit 0 PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed Note 1: 2: 3: 4: 5: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the module’s
PIC32MX1XX/2XX REGISTER 10-9: Bit Range 31:24 23:16 15:8 7:0 U1EIE: USB ERROR INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BTSEE BMXEE DMAEE BTOEE DFN8
PIC32MX1XX/2XX REGISTER 10-10: U1STAT: USB STATUS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-x R-x R-x R-x R-x R-x U-0 U-0 DIR PPBI — — ENDPT<3:0> Legend: R = Readable bit W = Writ
PIC32MX1XX/2XX REGISTER 10-11: U1CON: USB CONTROL REGISTER Bit Bit Bit Range 31/23/15/7 30/22/14/6 31:24 23:16 15:8 7:0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-x R-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 JSTATE SE0 PKTDIS(4) USBRST TOKBUSY(1,5) HOSTEN(2) RES
PIC32MX1XX/2XX REGISTER 10-11: U1CON: USB CONTROL REGISTER (CONTINUED) bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Even/Odd buffer pointers to the EVEN BD banks 0 = Even/Odd buffer pointers not being Reset bit 0 USBEN: USB Module Enable bit(4) 1 = USB module and supporting circuitry enabled 0 = USB module and supporting circuitry disabled SOFEN: SOF Enable bit(5) 1 = SOF token sent every 1 ms 0 = SOF token disabled Note 1: 2: 3: 4: 5: Software is required to check this bit before issuing a
PIC32MX1XX/2XX REGISTER 10-12: U1ADDR: USB ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPDEN DEVADDR<6:0> Legend: R = Readable bit
PIC32MX1XX/2XX REGISTER 10-14: U1FRMH: USB FRAME NUMBER HIGH REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 — — — — — FRMH<2:0> Legend: R = Readable bit
PIC32MX1XX/2XX REGISTER 10-16: U1SOF: USB SOF THRESHOLD REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT<7:0> Legend: R = Readable bit W = W
PIC32MX1XX/2XX REGISTER 10-18: U1BDTP2: USB BDT PAGE 2 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BDTPTRH<23:16> Legend: R = Readable bit
PIC32MX1XX/2XX REGISTER 10-20: U1CNFG1: USB CONFIGURATION 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 UTEYE UOEMON — USBSIDL — — — UASUSPND
PIC32MX1XX/2XX REGISTER 10-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPD RETRYDIS — EPCONDIS EPRX
PIC32MX1XX/2XX NOTES: DS61168E-page 140 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX 11.0 General purpose I/O pins are the simplest of peripherals. They allow the PIC® MCU to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin. I/O PORTS Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices.
PIC32MX1XX/2XX 11.1 11.1.4 Parallel I/O (PIO) Ports All port pins have ten registers directly associated with their operation as digital I/O. The data direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a ‘1’, then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx) read the latch. Writes to the latch write the latch.
PIC32MX1XX/2XX 11.3 Peripheral Pin Select A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The challenge is even greater on low pin-count devices. In an application where more than one peripheral needs to be assigned to a single pin, inconvenient workarounds in application code or a complete redesign may be the only option.
PIC32MX1XX/2XX TABLE 11-1: INPUT PIN SELECTION [pin name]R Value to RPn Pin Selection Peripheral Pin [pin name]R SFR [pin name]R bits INT4 INT4R INT4R<3:0> T2CK T2CKR T2CKR<3:0> IC4 IC4R IC4R<3:0> SS1 SS1R SS1R<3:0> REFCLKI REFCLKIR REFCLKIR<3:0> INT3 INT3R INT3R<3:0> T3CK T3CKR T3CKR<3:0> IC3 IC3R IC3R<3:0> U1CTS U1CTSR U1CTSR<3:0> U2RX U2RXR U2RXR<3:0> • • • SDI1 SDI1R SDI1R<3:0> 1111 = Reserved INT2 INT2R INT2R<3:0> T4CK T4CKR T4CKR<3:0> IC1 IC1R IC1R<3:0>
PIC32MX1XX/2XX 11.3.5 OUTPUT MAPPING 11.3.6.1 In contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPnR registers (Register 11-2) are used to control output mapping. Like the [pin name]R registers, each register contains sets of 4 bit fields.
PIC32MX1XX/2XX TABLE 11-2: OUTPUT PIN SELECTION RPnR Value to Peripheral Selection RPn Port Pin RPnR SFR RPnR bits RPA0 RPA0R RPA0R<3:0> RPB3 RPB3R RPB3R<3:0> RPB4 RPB4R RPB4R<3:0> RPB15 RPB15R RPB15R<3:0> RPB7 RPB7R RPB7R<3:0> RPC7 RPC7R RPC7R<3:0> RPC0 RPC0R RPC0R<3:0> RPC5 RPC5R RPC5R<3:0> RPA1 RPA1R RPA1R<3:0> RPB5 RPB5R RPB5R<3:0> RPB1 RPB1R RPB1R<3:0> RPB11 RPB11R RPB11R<3:0> RPB8 RPB8R RPB8R<3:0> RPA8 RPA8R RPA8R<3:0> RPC8 RPC8R RPC8R<3:0> RPA9 RPA9R
PIC32MX1XX/2XX REGISTER 11-1: Bit Range 31:24 23:16 15:8 7:0 [pin name]R: PERIPHERAL PIN SELECT INPUT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — [pin name]R<3:0> Legen
PIC32MX1XX/2XX REGISTER 11-3: Bit Range 31:24 23:16 15:8 7:0 CNCONx: CHANGE NOTICE CONTROL FOR PORTx REGISTER (x = A, B, C) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ON — SIDL — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — —
PIC32MX1XX/2XX 12.0 This family of PIC32 devices features one synchronous/asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applications and counting external events. This timer can also be used with the Low-Power Secondary Oscillator (SOSC) for Real-Time Clock (RTC) applications. The following modes are supported: TIMER1 Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices.
PIC32MX1XX/2XX REGISTER 12-1: Bit Range 31:24 23:16 15:8 7:0 T1CON: TYPE A TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 R/W-0 R-0 U-0 U-0 U-0 ON(1) — SIDL TWDIS TWIP — — — R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 TGATE — — TSYNC TCS
PIC32MX1XX/2XX REGISTER 12-1: T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED) bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer External Clock Input Synchronization Selection bit When TCS = 1: 1 = External clock input is synchronized 0 = External clock input is not synchronized When TCS = 0: This bit is ignored.
PIC32MX1XX/2XX NOTES: DS61168E-page 152 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX 13.0 Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes: TIMER2/3, TIMER4/5 Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14.
PIC32MX1XX/2XX FIGURE 13-2: TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT) Reset TMRy(1) MS Half Word ADC Event Trigger(2) Equal Sync LS Half Word 32-bit Comparator PRy TyIF Event Flag TMRx(1) PRx 0 1 TGATE Q D TGATE Q TCS ON TxCK x1 Gate Sync PBCLK 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS Note 1: 2: In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the use of ‘y’ in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 o
PIC32MX1XX/2XX REGISTER 13-1: Bit Range 31:24 23:16 15:8 7:0 TXCON: TYPE B TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ON(1,3) — SIDL(4) — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 T32(2) — TCS(3) — TGAT
PIC32MX1XX/2XX REGISTER 13-1: TXCON: TYPE B TIMER CONTROL REGISTER (CONTINUED) bit 3 T32: 32-Bit Timer Mode Select bit(2) 1 = Odd numbered and even numbered timers form a 32-bit timer 0 = Odd numbered and even numbered timers form a separate 16-bit timer bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timer Clock Source Select bit(3) 1 = External clock from TxCK pin 0 = Internal peripheral clock bit 0 Unimplemented: Read as ‘0’ Note 1: When using 1:1 PBCLK divisor, the user’s software should not read
PIC32MX1XX/2XX 14.0 • Capture timer value on every edge (rising and falling) • Capture timer value on every edge (rising and falling), specified edge first. • Prescaler capture event modes - Capture timer value on every 4th rising edge of input at ICx pin - Capture timer value on every 16th rising edge of input at ICx pin INPUT CAPTURE Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source.
PIC32MX1XX/2XX REGISTER 14-1: Bit Range Bit 31/23/15/7 Bit 30/22/14/6 U-0 U-0 31:24 23:16 15:8 7:0 ICXCON: INPUT CAPTURE ‘x’ CONTROL REGISTER Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 (1) U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 — SIDL — — — FEDGE C32 R/W-0 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 ICOV ICBNE ON ICTMR
PIC32MX1XX/2XX REGISTER 14-1: bit 2-0 Note 1: ICXCON: INPUT CAPTURE ‘x’ CONTROL REGISTER (CONTINUED) ICM<2:0>: Input Capture Mode Select bits 111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode) 110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter 101 = Prescaled Capture Event mode – every sixteenth rising edge 100 = Prescaled Capture Event mode – every fourth rising edge 011 = Simple Capture Event mode – every rising edge 010 = Simple Captur
PIC32MX1XX/2XX NOTES: DS61168E-page 160 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX 15.0 The Output Compare module (OCMP) is used to generate a single pulse or a train of pulses in response to selected time base events. For all modes of operation, the OCMP module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer. When a match occurs, the OCMP module generates an event based on the selected mode of operation. OUTPUT COMPARE Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices.
PIC32MX1XX/2XX REGISTER 15-1: Bit Range 31:24 23:16 15:8 7:0 OCxCON: OUTPUT COMPARE ‘x’ CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 (1) U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — SIDL — — — — — U-0 U-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OC32 OCFLT(2) OCTSEL
PIC32MX1XX/2XX 16.0 The SPI module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, Shift registers, display drivers, Analog-to-Digital Converters (ADC), etc. The PIC32 SPI module is compatible with Motorola® SPI and SIOP interfaces. SERIAL PERIPHERAL INTERFACE (SPI) Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices.
PIC32MX1XX/2XX REGISTER 16-1: Bit Range 31:24 23:16 15:8 7:0 SPIxCON: SPI CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 FRMCNT<2:0> R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 MCLKSEL(2) — — — — — SPIFE ENHBUF(2) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ON(1) — SIDL DISSDO MODE32 MODE16
PIC32MX1XX/2XX REGISTER 16-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED) bit 17 SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only) 1 = Frame synchronization pulse coincides with the first bit clock 0 = Frame synchronization pulse precedes the first bit clock bit 16 ENHBUF: Enhanced Buffer Enable bit(2) 1 = Enhanced Buffer mode is enabled 0 = Enhanced Buffer mode is disabled bit 15 ON: SPI Peripheral On bit(1) 1 = SPI Peripheral is enabled 0 = SPI Peripheral is disabled bit 14 Unimplemented: Re
PIC32MX1XX/2XX REGISTER 16-1: bit 4 SPIxCON: SPI CONTROL REGISTER (CONTINUED) DISSDI: Disable SDI bit 1 = SDI pin is not used by the SPI module (pin is controlled by PORT function) 0 = SDI pin is controlled by the SPI module STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits 11 = Interrupt is generated when the buffer is not full (has one or more empty elements) 10 = Interrupt is generated when the buffer is empty by one-half or more 01 = Interrupt is generated when the buffer is completely empty
PIC32MX1XX/2XX REGISTER 16-2: Bit Range 31:24 23:16 15:8 7:0 SPIxCON2: SPI CONTROL REGISTER 2 Bit 31/23/15/7 Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — U-0 — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPISGNEXT — — FRMERREN SPIROVEN R/W-0 U-0 U-0 U-0 R/W-0 U-0 AUDEN(1) — — — AUDMONO(1,2) — Legend
PIC32MX1XX/2XX REGISTER 16-3: Bit Range 31:24 23:16 15:8 7:0 SPIxSTAT: SPI STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 U-0 R-0 SPITUR — — — U-0 U-0 U-0 RXBUFELM<4:0> — — — U-0 U-0 U-0 R/C-0, HS R-0 R-0 TXBUFELM<4:0> U-0 — — — FRMERR SPIBUSY — — R-0 R/W-0 R-0 U-0 R-1 U-0 R-0 R-0 SRMT SPIROV SPIRBE — SPITBE — SP
PIC32MX1XX/2XX REGISTER 16-3: SPIxSTAT: SPI STATUS REGISTER bit 3 SPITBE: SPI Transmit Buffer Empty Status bit 1 = Transmit buffer, SPIxTXB is empty 0 = Transmit buffer, SPIxTXB is not empty Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR. Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB.
PIC32MX1XX/2XX NOTES: DS61168E-page 170 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX 17.0 INTER-INTEGRATED CIRCUIT™ (I2C™) Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. “InterIntegrated Circuit™ (I2C™)” (DS61116) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX1XX/2XX FIGURE 17-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2CxRCV SCLx Read Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control Write BRG Down Counter I2CxBRG Read PBCLK DS61168E-page 172 Preliminary 2011-2012 Micro
PIC32MX1XX/2XX REGISTER 17-1: Bit Range 31:24 23:16 15:8 7:0 I2CXCON: I2C™ CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 (1) U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 — SIDL SCLREL STRICT A10M DISSLW SMEN R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W
PIC32MX1XX/2XX REGISTER 17-1: I2CXCON: I2C™ CONTROL REGISTER (CONTINUED) bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit.
PIC32MX1XX/2XX REGISTER 17-2: Bit Range 31:24 23:16 15:8 7:0 I2CXSTAT: I2C™ STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, H
PIC32MX1XX/2XX REGISTER 17-2: I2CXSTAT: I2C™ STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected.
PIC32MX1XX/2XX 18.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS61107) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX1XX/2XX REGISTER 18-1: Bit Range 31:24 23:16 15:8 7:0 UxMODE: UARTx MODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 (1) U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 — SIDL IREN RTSMD — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH ON UEN<1:
PIC32MX1XX/2XX REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 5 ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character – requires reception of Sync character (0x55); cleared by hardware upon completion 0 = Baud rate measurement disabled or completed bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode – 4x baud clock enabled 0 = Standard Speed mode – 16x baud
PIC32MX1XX/2XX REGISTER 18-2: Bit Range 31:24 23:16 15:8 7:0 UxSTA: UARTx STATUS AND CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — ADM_EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR<7:0> R/W-0 R/W-0 UTXISEL<1:0> R/W-0 R/W-0 URXISEL<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-1 UTXINV URXEN UTXBRK UTXEN UTXBF TRMT R/W-0 R-
PIC32MX1XX/2XX REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bit 11 = Reserved; do not use 10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full (i.e., has 6 or more data characters) 01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full (i.e., has 4 or more data characters) 00 = Interrupt flag bit is asserted while receive buffer is not empty (i.e.
PIC32MX1XX/2XX Figure 18-2 and Figure 18-3 illustrate typical receive and transmit timing for the UART module.
PIC32MX1XX/2XX 19.0 Key features of the PMP module include: PARALLEL MASTER PORT (PMP) Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. “Parallel Master Port (PMP)” (DS61128) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX1XX/2XX REGISTER 19-1: Bit Range 31:24 23:16 15:8 PMCON: PARALLEL PORT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 (1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SIDL ADRMUX<1:0> PMPTTL PTWREN PTRDEN R/W-0 R/W-0 (2) R/W-0 (2) U-0 U-0 R/W-0 R/W-0 — W
PIC32MX1XX/2XX REGISTER 19-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) bit 4 Unimplemented: Read as ‘0’ bit 3 CS1P: Chip Select 0 Polarity bit(2) 1 = Active-high (PMCS1) 0 = Active-low (PMCS1) bit 2 Unimplemented: Read as ‘0’ bit 1 WRSP: Write Strobe Polarity bit For Slave Modes and Master mode 2 (PMMODE<9:8> = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master mode 1 (PMMODE<9:8> = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe activ
PIC32MX1XX/2XX REGISTER 19-2: Bit Range 31:24 23:16 15:8 PMMODE: PARALLEL PORT MODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 BUSY R/W-0 7:0 IRQM<1:0> R/W-0 (1) INCM<1:0> R/W-0 R/W-0 WAITB<1:0> R/W-0 (1) — MODE<1:0> R/W-0 R/W-
PIC32MX1XX/2XX REGISTER 19-2: PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED) bit 5-2 WAITM<3:0>: Data Read/Write Strobe Wait States bits(1) 1111 = Wait of 16 TPB • • • 0001 = Wait of 2 TPB 0000 = Wait of 1 TPB (default) bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits(1) 11 = Wait of 4 TPB 10 = Wait of 3 TPB 01 = Wait of 2 TPB 00 = Wait of 1 TPB (default) For Read operations: 11 = Wait of 3 TPB 10 = Wait of 2 TPB 01 = Wait of 1 TPB 00 = Wait of 0 TPB (default) Note 1: Whenever W
PIC32MX1XX/2XX REGISTER 19-3: Bit Range 31:24 23:16 15:8 7:0 PMADDR: PARALLEL PORT ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — CS1 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR<10:8> R/W-0 R/W-0 R/W-0 ADDR<7:0> Legend: R = Re
PIC32MX1XX/2XX REGISTER 19-4: Bit Range 31:24 23:16 15:8 7:0 PMAEN: PARALLEL PORT PIN ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — PTEN14 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN<10:8> R/W-0 R/W-0 R/W-0 PTEN<7:0> Legend:
PIC32MX1XX/2XX REGISTER 19-5: Bit Range 31:24 23:16 15:8 7:0 PMSTAT: PARALLEL PORT STATUS REGISTER (SLAVE MODES ONLY) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R/W-0, HSC U-0 U-0 R-0 R-0 R-0 R-0 IB0F IBF IBOV — — IB3F IB2F IB1F R-1 R/W-0, HSC U-0 U-0 R-1 R-1 R-1 R-1 OBE
PIC32MX1XX/2XX 20.0 Following are some of the key features of this module: REAL-TIME CLOCK AND CALENDAR (RTCC) • • • • Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. “Real-Time Clock and Calendar (RTCC)” (DS61125) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX1XX/2XX REGISTER 20-1: Bit Range 31:24 23:16 Bit 31/23/15/7 Bit 30/22/14/6 U-0 U-0 Bit Bit 29/21/13/5 28/20/12/4 U-0 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL<9:8> R/W-0 U-0 U-0 U-0 U-0 CAL<7:0> 15:8 7:0 RTCCON: RTC CONTROL REGISTER R/W-0 (1,2) U-0 R/W-0 — SIDL — — — — — R/W-0 R-0 U-0 U-0 R/W-0 R-0 R-0 R/W-0 — — ON RTSECSEL(3) RTCCLKON U-0 RTCWRE
PIC32MX1XX/2XX REGISTER 20-1: RTCCON: RTC CONTROL REGISTER (CONTINUED) bit 5-4 Unimplemented: Read as ‘0’ bit 3 RTCWREN: RTC Value Registers Write Enable bit(4) 1 = RTC Value registers can be written to by the user 0 = RTC Value registers are locked out from being written to by the user bit 2 RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data read If the register is read twice and results in
PIC32MX1XX/2XX REGISTER 20-2: Bit Range 31:24 23:16 15:8 7:0 RTCALRM: RTC ALARM CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R-0 R/W-0 R/W-0 CHIME(2) R/W-0 (2) R/W-0 ALRMEN(1,2) R/W-0 (2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PIV ALRMSYNC(3) R/W-0 AMASK<3:
PIC32MX1XX/2XX REGISTER 20-2: RTCALRM: RTC ALARM CONTROL REGISTER (CONTINUED) ARPT<7:0>: Alarm Repeat Counter Value bits(2) 11111111 = Alarm will trigger 256 times bit 7-0 • • • 00000000 = Alarm will trigger one time The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1. Note 1: 2: 3: Note: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0.
PIC32MX1XX/2XX REGISTER 20-3: Bit Range 31:24 23:16 15:8 7:0 RTCTIME: RTC TIME VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10<3:0> HR01<3:0> R/W-x MIN10<3:0> R/W-x R/W-x U-0 U-0 — — R/W-x R/W-x MIN01<3:0> R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — SEC10<3:0> R/W-x R/W-x S
PIC32MX1XX/2XX REGISTER 20-4: Bit Range 31:24 23:16 15:8 7:0 RTCDATE: RTC DATE VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YEAR10<3:0> R/W-x R/W-x YEAR01<3:0> R/W-x R/W-x R/W-x MONTH10<3:0> R/W-x R/W-x R/W-x R/W-x R/W-x MONTH01<3:0> R/W-x R/W-x R/W-x R/W-x DAY10<3:0> R/W-x R/W-x DAY01<3:0> U-0 U-0 U-0 U-0 — — — — R/W-x R/W-x
PIC32MX1XX/2XX REGISTER 20-5: Bit Range 31:24 23:16 15:8 7:0 ALRMTIME: ALARM TIME VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10<3:0> HR01<3:0> R/W-x MIN10<3:0> R/W-x R/W-x U-0 U-0 — — R/W-x R/W-x MIN01<3:0> R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — SEC10<3:0> R/W-x R/W-x
PIC32MX1XX/2XX REGISTER 20-6: Bit Range 31:24 23:16 15:8 7:0 ALRMDATE: ALARM DATE VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-x R/W-x R/W-x R/W-x R/W-x MONTH10<3:0> R/W-x R/W-x Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — R/W-x R/W-x R/W-x MONTH01<3:0> R/W-x R/W-x R/W-x R/W-x DAY10<1:0> R/W-x R/W-x DAY01<3:0> U-0 U-0 U-0 U-0 — — — — R/W-x R/W-x R/W-x R/W-x W
PIC32MX1XX/2XX NOTES: DS61168E-page 200 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX 21.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS61104) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX1XX/2XX FIGURE 21-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADRC FRC(1) Div 2 1 TAD ADCS<7:0> 0 8 ADC Conversion Clock Multiplier TPB(2) 2, 4,..., 512 Note 1: 2: DS61168E-page 202 See Section 29.0 “Electrical Characteristics” for the exact FRC clock value. Refer to Figure 8-1 in Section 8.0 “Oscillator Configuration” for more information. Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX REGISTER 21-1: Bit Range 31:24 23:16 15:8 7:0 AD1CON1: ADC CONTROL REGISTER 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 (1) U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — SIDL — — R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 CLRASAM — ASAM ON SSRC<2:0> FORM<2:0> R/W-0, HSC (
PIC32MX1XX/2XX REGISTER 21-1: AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED) bit 4 CLRASAM: Stop Conversion Sequence bit (when the first ADC interrupt is generated) 1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the ADC interrupt is generated.
PIC32MX1XX/2XX REGISTER 21-2: Bit Range 31:24 23:16 15:8 AD1CON2: ADC CONTROL REGISTER 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 OFFCAL — CSCNA — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFM ALTS VCFG<2:0> 7:0 Bit Bit 28/20/12/4 27/19/11/3 R-0 U-0 BUFS — R/W-0 SMPI<
PIC32MX1XX/2XX REGISTER 21-3: Bit Range 31:24 23:16 15:8 7:0 AD1CON3: ADC CONTROL REGISTER 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 U-0 — — — — R/W-0 U-0 U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC — — R/W-0 R/W-0 R/W-0 R/W R/W-0 SAMC<4:0>(1) R/W-0 R/W-0 R/W-0 ADCS<7:0>(2) Legend: R = Readabl
PIC32MX1XX/2XX REGISTER 21-4: Bit Range 31:24 23:16 15:8 7:0 AD1CHS: ADC INPUT SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 U-0 U-0 U-0 CH0NB — — — R/W-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 CH0SB<3:0> R/W-0 R/W-0 R/W-0 R/W-0 CH0NA — — — U-0 U-0 U-0 U-0 U-0 U-0 CH0SA<3:0> U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 Legend:
PIC32MX1XX/2XX REGISTER 21-5: Bit Range 31:24 23:16 15:8 7:0 AD1CSSL: ADC INPUT SCAN SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/
PIC32MX1XX/2XX 22.0 The PIC32MX1XX/2XX Analog Comparator module contains three comparators that can be configured in a variety of ways. COMPARATOR Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. “Comparator” (DS61110) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX1XX/2XX REGISTER 22-1: Bit Range 31:24 23:16 15:8 7:0 CMXCON: COMPARATOR CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 U-0 — — — — R/W-0 (1) R/W-0 — U-0 U-0 U-0 U-0 R-0 ON COE — — — — COUT R/W-1 R/W-1 U-0 R/W-0 U-0 U-0 R/W-1 — CREF — — R/W-0 (2) CPOL EVPOL<1:0> R/W
PIC32MX1XX/2XX REGISTER 22-2: Bit Range 31:24 23:16 15:8 7:0 CMSTAT: COMPARATOR STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — SIDL — — — — — U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 — — — — — C3OUT C2OUT C1OUT Legend: R = Reada
PIC32MX1XX/2XX NOTES: DS61168E-page 212 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX 23.0 The CVREF module is a 16-tap, resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. COMPARATOR VOLTAGE REFERENCE (CVREF) Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 20.
PIC32MX1XX/2XX REGISTER 23-1: Bit Range 31:24 23:16 15:8 7:0 CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 (1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 ON U-0 R/W-0 R/W-0 R/W-0 — CVROE CVRR
PIC32MX1XX/2XX 24.0 on-chip analog modules, the CTMU can be used for high resolution time measurement, measure capacitance, measure relative changes in capacitance or generate output pulses with a specific time delay. The CTMU is ideal for interfacing with capacitive-based sensors. CHARGE TIME MEASUREMENT UNIT (CTMU) Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source.
PIC32MX1XX/2XX REGISTER 24-1: Bit Range 31:24 23:16 15:8 7:0 CTMUCON: CTMU CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 EDG1MOD EDG1POL R/W-0 R/W-0 R/W-0 Bit 26/18/10/2 R/W-0 EDG1SEL<3:0> R/W-0 R/W-0 EDG2MOD EDG2POL R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 EDG2STAT EDG1STAT R/W-0 U-0 EDG2SEL<3:0> U-0 — — R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ON — CTMUSIDL TGEN(1) EDGEN EDGSEQEN IDISSE
PIC32MX1XX/2XX REGISTER 24-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 24 EDG1STAT: Edge1 Status bit Indicates the status of Edge1 and can be written to control edge source 1 = Edge1 has occurred 0 = Edge1 has not occurred bit 23 EDG2MOD: Edge2 Edge Sampling Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive bit 22 EDG2POL: Edge 2 Polarity Select bit 1 = Edge2 programmed for a positive edge response 0 = Edge2 programmed for a negative edge response bit 21-18 EDG2SEL<3:0>: Edge 2 So
PIC32MX1XX/2XX REGISTER 24-1: bit 10 CTMUCON: CTMU CONTROL REGISTER (CONTINUED) EDGSEQEN: Edge Sequence Enable bit 1 = Edge1 must occur before Edge2 can occur 0 = No edge sequence is needed IDISSEN: Analog Current Source Control bit(2) 1 = Analog current source output is grounded 0 = Analog current source output is not grounded CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current
PIC32MX1XX/2XX 25.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. “PowerSaving Features” (DS61130) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices.
PIC32MX1XX/2XX The processor will exit, or ‘wake-up’, from Sleep on one of the following events: • On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority.
PIC32MX1XX/2XX 25.4 To disable a peripheral, the associated PMDx bit must be set to ‘1’. To enable a peripheral, the associated PMDx bit must be cleared (default). See Table 25-1 for more information. Peripheral Module Disable The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled using the appropriate PMD control bit, the peripheral is in a minimum power consumption state.
PIC32MX1XX/2XX 25.4.1 CONTROLLING CONFIGURATION CHANGES Because peripherals can be disabled during run time, some restrictions on disabling peripherals are needed to prevent accidental configuration changes. PIC32 devices include two features to prevent alterations to enabled or disabled peripherals: • Control register lock sequence • Configuration bit select lock 25.4.1.1 Control Register Lock Under normal operation, writes to the PMDx registers are not allowed.
PIC32MX1XX/2XX 26.0 Note: SPECIAL FEATURES This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog Timer and Power-up Timer” (DS61114), Section 32. “Configuration” (DS61124) and Section 33. “Programming and Diagnostics” (DS61129) in the “PIC32 Family Reference Manual” (DS61132), which is available from the Microchip web site (www.
PIC32MX1XX/2XX REGISTER 26-1: Bit Range DEVCFG0: DEVICE CONFIGURATION WORD 0 Bit 31/23/15/7 31:24 23:16 15:8 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 24/16/8/0 r-0 r-1 r-1 R/P r-1 r-1 r-1 R/P — — — CP — — — BWP r-1 r-1 r-1 r-1 r-1 r-1 r-1 R/P — — — — — — — PWP<6> R/P R/P R/P R/P R/P R/P PWP<5:0> 7:0 Bit 25/17/9/1 r-1 r-1 r-1 R/P — — — ICESEL<1:0>(2) Legend: R = Readable bit -n = Value at POR r = Reserved bit W
PIC32MX1XX/2XX REGISTER 26-1: bit 9-5 bit 4-3 bit 2 bit 1-0 Note 1: 2: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED) Reserved: Write ‘1’ ICESEL<1:0>: In-Circuit Emulator/Debugger Communication Channel Select bits 11 = PGEC1/PGED1 pair is used 10 = PGEC2/PGED2 pair is used 01 = PGEC3/PGED3 pair is used 00 = PGEC4/PGED4 pair is used(2) JTAGEN: JTAG Enable bit(1) 1 = JTAG is enabled 0 = JTAG is disabled DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled) 1x = Debugge
PIC32MX1XX/2XX REGISTER 26-2: Bit Range 31:24 23:16 15:8 7:0 DEVCFG1: DEVICE CONFIGURATION WORD 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 R/P R/P — — — — — — R/P R/P r-1 R/P R/P R/P FWDTEN WINDIS — R/P R/P R/P FCKSM<1:0> FWDTWINSZ<1:0> R/P R/P R/P R/P WDTPS<4:0> R/P FPBDIV<1:0> r-1 R/P — OSCIOFNC R/P r-1 R/P r-1 r-1 R/P IESO — FSOSCEN — — POSCMOD<1:0
PIC32MX1XX/2XX REGISTER 26-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED) bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = P
PIC32MX1XX/2XX REGISTER 26-3: Bit Range 31:24 23:16 15:8 7:0 DEVCFG2: DEVICE CONFIGURATION WORD 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 r-1 r-1 r-1 r-1 r-1 — — — — — — — — r-1 r-1 r-1 r-1 r-1 R/P R/P R/P — — — — — R/P r-1 r-1 r-1 r-1 UPLLEN r-1 (1) Bit Bit 28/20/12/4 27/19/11/3 — — — — R/P-1 R/P R/P-1 r-1 — FPLLMUL<2:0> r = Reserved bit Legend: Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 FPLLODIV<2:0> R/P R/P R/P (1) UPLLIDIV<2:0>
PIC32MX1XX/2XX REGISTER 26-3: DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED) bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider Note 1: This bit is available on PIC32MX2XX devices only. 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX REGISTER 26-4: Bit Range 31:24 23:16 15:8 7:0 DEVCFG3: DEVICE CONFIGURATION WORD 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/P R/P R/P R/P r-1 r-1 r-1 r-1 FVBUSONIO FUSBIDIO IOL1WAY PMDL1WAY — — — — r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P USERID<15:8> R/P Legend: R = Readable bit -n = Value at POR R/P R/P R/P
PIC32MX1XX/2XX REGISTER 26-5: Bit Range 31:24 23:16 15:8 7:0 CFGCON: CONFIGURATION CONTROL REGISTER Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — — — — — — U-0 U-0 U-0 U-0 R/W-1 U-0 U-1 R/W-1 — — — — JTAGEN — — TDOEN IOLOCK(1) PMDLOCK(
PIC32MX1XX/2XX REGISTER 26-6: Bit Range 31:24 23:16 15:8 7:0 DEVID: DEVICE AND REVISION ID REGISTER Bit 31/23/15/7 Bit 30/22/14/6 R R R R Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 R (1) R R R R R R (1) Bit 25/17/9/1 Bit 24/16/8/0 R (1) R R R R R (1) R R R R R R R VER<3:0> DEVID<27:24> DEVID<23:16> R R R R R R R DEVID<15:8> R DEVID<7:0>(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit
PIC32MX1XX/2XX 26.2 Watchdog Timer (WDT) This section describes the operation of the WDT and Power-up Timer of the PIC32MX1XX/2XX. The WDT, when enabled, operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode.
PIC32MX1XX/2XX REGISTER 26-7: Bit Range 31:24 23:16 15:8 7:0 WDTCON: WATCHDOG TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 ON(1,2) — — — — — — — U-0 R-y R-y R-y R-y R-y R/W-0 R/W-0 — SWDTPS<4:0> WDTWINEN WDTCLR y = Val
PIC32MX1XX/2XX 26.3 On-Chip Voltage Regulator 26.4 All PIC32MX1XX/2XX devices’ core and digital logic are designed to operate at a nominal 1.8V. To simplify system designs, most devices in the PIC32MX1XX/2XX family incorporate an on-chip regulator providing the required core logic voltage from VDD. A low-ESR capacitor (such as tantalum) must be connected to the VCAP pin (see Figure 26-2). This helps to maintain the stability of the regulator.
PIC32MX1XX/2XX NOTES: DS61168E-page 236 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX 27.0 INSTRUCTION SET The PIC32MX1XX/2XX family instruction set complies with the MIPS32® Release 2 instruction set architecture. The PIC32 device family does not support the following features: • Core extend instructions • Coprocessor 1 instructions • Coprocessor 2 instructions Note: Refer to “MIPS32® Architecture for Programmers Volume II: The MIPS32® Instruction Set” at www.mips.com for more information. 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX NOTES: DS61168E-page 238 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX 28.0 DEVELOPMENT SUPPORT ® 28.
PIC32MX1XX/2XX 28.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 28.
PIC32MX1XX/2XX 28.7 MPLAB SIM Software Simulator 28.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC32MX1XX/2XX 28.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 28.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC32MX1XX/2XX 29.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC32MX1XX/2XX electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MX1XX/2XX devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
PIC32MX1XX/2XX 29.1 DC Characteristics TABLE 29-1: OPERATING MIPS VS. VOLTAGE Max. Frequency VDD Range (in Volts)(1) Temp. Range (in °C) PIC32MX1XX/2XX DC5 2.3-3.6V -40°C to +85°C 40 MHz DC5b 2.3-3.6V -40°C to +105°C 40 MHz Characteristic Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN.
PIC32MX1XX/2XX TABLE 29-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typ. Max. Units Conditions Operating Voltage DC10 VDD Supply Voltage (Note 2) 2.3 — 3.6 V — DC12 VDR RAM Data Retention Voltage (Note 1) 1.
PIC32MX1XX/2XX TABLE 29-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp DC CHARACTERISTICS Parameter No. Typical(3) Max. Units Conditions Operating Current (IDD) (Note 1, 2) DC20 2 3 mA 4 MHz (Note 4) DC21 7 10.
PIC32MX1XX/2XX TABLE 29-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp DC CHARACTERISTICS Parameter No. Typical(2) Max. Units Conditions Idle Current (IIDLE): Core Off, Clock on Base Current (Note 1) DC30a 1 1.5 mA 4 MHz (Note 3) DC31a 2 3 mA 10 MHz DC32a 4 6 mA 20 MHz (Note 3) DC33a 5.5 8 mA 30 MHz (Note 3) DC34a 7.
PIC32MX1XX/2XX TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) DC CHARACTERISTICS Param. Typical(2) No. Max. Standard Operating Conditions: 2.3V to 3.
PIC32MX1XX/2XX TABLE 29-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param. Symbol No. VIL DI10 Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp Min. Typical(1) Max. Units Conditions Input Low Voltage I/O Pins with PMP VSS — 0.15 VDD V I/O Pins VSS — 0.2 VDD V DI18 SDAx, SCLx VSS — 0.
PIC32MX1XX/2XX TABLE 29-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp DC CHARACTERISTICS Param. Symbol Characteristic Min. Typ. Max. Units Conditions — — 0.4 V IOL 10 mA, VDD = 3.3V Output High Voltage 1.5(1) — — I/O Pins 2.0(1) — — 2.4 — — 3.
PIC32MX1XX/2XX TABLE 29-11: DC CHARACTERISTICS: PROGRAM MEMORY DC CHARACTERISTICS Param. Symbol No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp Min. Typical(1) Max. Units Conditions Program Flash Memory(3) EP Cell Endurance 20,000 — — E/W — D131 VPR VDD for Read 2.3 — 3.6 V — D132 VPEW VDD for Erase or Write 2.3 — 3.
PIC32MX1XX/2XX TABLE 29-12: COMPARATOR SPECIFICATIONS Standard Operating Conditions (see Note 4): 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical Max. Units Comments D300 VIOFF Input Offset Voltage — ±7.
PIC32MX1XX/2XX 29.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC32MX1XX/2XX AC characteristics and timing parameters.
PIC32MX1XX/2XX TABLE 29-15: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. Symbol No. Min. Typical(1) Max.
PIC32MX1XX/2XX TABLE 29-16: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical Max. Units Conditions OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range 3.
PIC32MX1XX/2XX FIGURE 29-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) DO31 DO32 Note: Refer to Figure 29-1 for load conditions. TABLE 29-19: I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. No. Symbol Characteristics(2) Min. Typical(1) Max. Units — 5 15 ns VDD < 2.
PIC32MX1XX/2XX FIGURE 29-4: POWER-ON RESET TIMING CHARACTERISTICS Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) CPU Starts Fetching Code SY00 (TPU) (Note 1) Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) SY00 (TPU) (Note 1) Note 1: 2: SY10 (TOST) CPU Starts Fetching Code The power-up period will be exte
PIC32MX1XX/2XX FIGURE 29-5: EXTERNAL RESET TIMING CHARACTERISTICS Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) MCLR TMCLR (SY20) BOR TBOR (SY30) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code TOST (SY10) TABLE 29-20: RESETS TIMING Standard Operating Conditions: 2.3V to 3.
PIC32MX1XX/2XX FIGURE 29-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 Tx20 OS60 TMRx Note: Refer to Figure 29-1 for load conditions. TABLE 29-21: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS(1) Param. No.
PIC32MX1XX/2XX TABLE 29-22: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Max. Units TB10 TTXH TxCK Synchronous, with High Time prescaler [(12.5 ns or 1 TPB)/N] + 25 ns — ns TB11 TTXL TxCK Synchronous, with Low Time prescaler [(12.
PIC32MX1XX/2XX FIGURE 29-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM mode) OC10 OC11 Note: Refer to Figure 29-1 for load conditions. TABLE 29-24: OUTPUT COMPARE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical(2) Max.
PIC32MX1XX/2XX FIGURE 29-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP31 SDIx LSb SP30 MSb In LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 29-1 for load conditions. TABLE 29-26: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX1XX/2XX FIGURE 29-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SCKX (CKP = 1) SP10 SP21 SP20 SP20 SP21 SP35 LSb Bit 14 - - - - - -1 MSb SDOX SP30,SP31 SDIX MSb In SP40 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 29-1 for load conditions. TABLE 29-27: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX1XX/2XX FIGURE 29-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX LSb Bit 14 - - - - - -1 SP51 SP30,SP31 SDIX Bit 14 - - - -1 MSb In SP40 LSb In SP41 Note: Refer to Figure 29-1 for load conditions. TABLE 29-28: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX1XX/2XX FIGURE 29-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In SP40 SP51 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 29-1 for load conditions. TABLE 29-29: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX1XX/2XX TABLE 29-29: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical(2) Max.
PIC32MX1XX/2XX FIGURE 29-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 29-1 for load conditions. FIGURE 29-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 29-1 for load conditions. 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX TABLE 29-30: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. Symbol No. IM10 IM11 IM20 Min.(1) Max.
PIC32MX1XX/2XX TABLE 29-30: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. Symbol No. IM40 IM45 TAA:SCL Min.(1) Max.
PIC32MX1XX/2XX FIGURE 29-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition Note: Refer to Figure 29-1 for load conditions. FIGURE 29-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out Note: Refer to Figure 29-1 for load conditions. DS61168E-page 270 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX TABLE 29-31: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. No. IS10 IS11 IS20 Symbol TLO:SCL THI:SCL TF:SCL Characteristics Clock Low Time Clock High Time SDAx and SCLx Fall Time Min. Max. Units 100 kHz mode 4.7 — s PBCLK must operate at a minimum of 800 kHz 400 kHz mode 1.
PIC32MX1XX/2XX TABLE 29-31: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. No. IS34 IS40 Symbol THD:STO TAA:SCL Characteristics Stop Condition Hold Time Min.
PIC32MX1XX/2XX TABLE 29-32: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions (see Note 5): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp Characteristics Min. Typical Max. Units Conditions — Device Supply AD01 AVDD Module VDD Supply Greater of VDD – 0.3 or 2.5 — Lesser of VDD + 0.3 or 3.6 V AD02 AVSS Module VSS Supply VSS — AVDD V (Note 1) — — AVDD 3.
PIC32MX1XX/2XX TABLE 29-32: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param. Symbol No. Characteristics Standard Operating Conditions (see Note 5): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp Min. Typical Max. Units Conditions ADC Accuracy – Measurements with Internal VREF+/VREFAD20d Nr Resolution AD21d INL Integral Non-linearity > -1 — <1 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.
PIC32MX1XX/2XX TABLE 29-33: 10-BIT CONVERSION RATE PARAMETERS AC Standard Operating Conditions (see Note 3): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp CHARACTERISTICS(2) ADC Speed TAD Min. Sampling Time Min. RS Max. VDD 1 Msps to 400 ksps(1) 65 ns 132 ns 500 3.0V to 3.6V ADC Channels Configuration VREF- VREF+ ANx Up to 400 ksps 200 ns 200 ns 5.0 k CHX SHA 2.5V to 3.
PIC32MX1XX/2XX TABLE 29-34: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS Standard Operating Conditions (see Note 4): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. Symbol No. Min. Typical(1) Max.
PIC32MX1XX/2XX FIGURE 29-18: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp eoc AD61 AD60 AD55 TSAMP AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets ADxCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 17.
PIC32MX1XX/2XX FIGURE 29-19: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Execution Set ADON SAMP ch0_dischrg ch0_samp eoc TSAMP AD55 TSAMP AD55 TCONV CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 – Software sets ADxCON. ADON to start AD operation. 5 – Convert bit 0. 2 – Sampling starts after discharge period. TSAMP is described in Section 17.
PIC32MX1XX/2XX FIGURE 29-20: PARALLEL SLAVE PORT TIMING CS PS5 RD PS6 WR PS4 PS7 PMD<7:0> PS1 PS3 PS2 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX TABLE 29-35: PARALLEL SLAVE PORT REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Para Symbol m.No. Characteristics(1) Min. Typ. Max.
PIC32MX1XX/2XX TABLE 29-36: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typ. Max.
PIC32MX1XX/2XX TABLE 29-37: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typ. Max.
PIC32MX1XX/2XX TABLE 29-39: CTMU CURRENT SOURCE SPECIFICATIONS DC CHARACTERISTICS Param No. Symbol Standard Operating Conditions (see Note 3):2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp Characteristic Min. Typ. Max. Units Conditions CTMU CURRENT SOURCE CTMUI1 IOUT1 Base Range(1) — 0.55 — µA CTMUICON<9:8> = 01 CTMUI2 IOUT2 10x Range(1) — 5.
PIC32MX1XX/2XX FIGURE 29-23: EJTAG TIMING CHARACTERISTICS TTCKeye TTCKhigh TTCKlow Trf TCK Trf TMS TDI TTsetup TThold Trf Trf TDO TRST* TTRST*low TTDOout TTDOzstate Defined Trf Undefined TABLE 29-40: EJTAG TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. No. Symbol Description(1) Min. Max.
PIC32MX1XX/2XX 30.0 50 MHz ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC32MX1XX/2XX electrical characteristics for devices operating at 50 MHz. The specifications for 50 MHz are identical to those shown in Section 29.0 “Electrical Characteristics”, with the exception of the parameters listed in this chapter. Parameters in this chapter begin with the letter “M”, which denotes 50 MHz operation. For example, parameter DC29a in Section 29.
PIC32MX1XX/2XX 30.1 DC Characteristics TABLE 30-1: OPERATING MIPS VS. VOLTAGE Characteristic Temp. Range (in °C) PIC32MX1XX/2XX 2.3-3.6V -40°C to +85°C 50 MHz MDC5 Note 1: Max. Frequency VDD Range (in Volts)(1) Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to parameter BO10 in Table 29-10 for BOR values.
PIC32MX1XX/2XX TABLE 30-3: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(2) Max. Units Conditions Idle Current (IIDLE): Core Off, Clock on Base Current (Note 1) MDC34a Note 1: 2: 8 13 TABLE 30-4: 50 MHz DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.3V to 3.
PIC32MX1XX/2XX TABLE 30-5: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS Param. Symbol No. MOS10 FOSC Note 1: 2: Characteristics External CLKI Frequency (External clocks allowed only in EC and ECPLL modes) Typical Max.
PIC32MX1XX/2XX TABLE 30-8: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp AC CHARACTERISTICS Param. No. Symbol Min. Typ. Max. Units Conditions TSCK/2 TSCK/2 — — — — ns ns — — MSP51 TSSH2DOZ SSx to SDOx Output 5 — 25 High-Impedance (Note 2) Note 1: These parameters are characterized, but not tested in manufacturing.
PIC32MX1XX/2XX NOTES: DS61168E-page 290 Preliminary 2011-2012 Microchip Technology Inc.
2011-2012 Microchip Technology Inc. 30.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
FIGURE 30-5: TYPICAL IPD CURRENT @ VDD = 3.3V TYPICAL IIDLE CURRENT @ VDD = 3.3V PIC32MX1XX/2XX 8 400 7 350 6 300 IID DLE Current (mA) DS61168E-page 292 FIGURE 30-3: IPD (µA) 250 200 150 100 5 4 3 2 50 1 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (Celsius) 0 Preliminary 0 10 20 MIPS FIGURE 30-4: TYPICAL IDD CURRENT @ VDD = 3.3V 25 2011-2012 Microchip Technology Inc.
FIGURE 30-8: TYPICAL FRC FREQUENCY @ VDD = 3.3V TYPICAL CTMU TEMPERATURE DIODE FORWARD VOLTAGE 8000 7990 0.850 7980 0.800 0.750 7970 Forward Voltage (V) FRC Frequency (kHz) 2011-2012 Microchip Technology Inc. FIGURE 30-6: 7960 7950 7940 7930 0.650 55 µ A, VF VR 5 .5 µ VF = 0.658 0.600 = -1.5 A, V VF = 0.598 6 mV FVR 0.55 0.550 0.500 0 500 7920 0.450 7910 0.400 7900 VF = 0.721 0.700 = -1 µA , /ºC .7 4 m VFV R V / ºC = -1 . 92 mV / ºC 0.
PIC32MX1XX/2XX NOTES: DS61168E-page 294 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX 31.0 PACKAGING INFORMATION 31.1 Package Marking Information 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN PIC32MX220F 032B-I/SO e3 1130235 28-Lead SPDIP Example PIC32MX220F 032B-I/SP e3 1130235 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN PIC32MX220F 032B-I/SS e3 1130235 28-Lead QFN Example XXXXXXXX XXXXXXXX YYWWNNN Legend: XX...
PIC32MX1XX/2XX 31.1 Package Marking Information (Continued) 36-Lead VTLA Example XXXXXXXX XXXXXXXX YYWWNNN 32MX220F 032CE/TL e3 1130235 44-Lead VTLA Example PIC32 MX120F0 32DI/TL e3 1130235 XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead QFN Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 32MX220F 032D-E/ML 1130235 44-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...
PIC32MX1XX/2XX 31.2 Package Details This section provides the technical details of the packages.
PIC32MX1XX/2XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61168E-page 298 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX /HDG 6NLQQ\ 3ODVWLF 'XDO ,Q /LQH 63 ± PLO %RG\ >63',3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV ,1&+(6 0,1 1 120 0$; 3LWFK H 7RS WR 6HDWLQJ 3ODQH $ ± ± 0ROGHG 3DFNDJH 7KLFNQHVV $ %DVH WR 6HDWLQJ 3ODQH $ ± ± 6KRXOGHU WR 6KRXOGHU :LGWK (
PIC32MX1XX/2XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61168E-page 300 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61168E-page 302 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ PP %RG\ >4)1@ ZLWK PP &RQWDFW /HQJWK 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D2 EXPOSED PAD e E b E2 2 2 1 1 N K N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ 6WDQGRII $ &RQWDFW 7KLFN
PIC32MX1XX/2XX /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ PP %RG\ >4)1@ ZLWK PP &RQWDFW /HQJWK 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS61168E-page 304 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX DS61168E-page 306 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX DS61168E-page 308 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ PP %RG\ >4)1@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ 6WDQGRII $ &RQWDFW 7KLFNQHVV $ 2YHUDOO :LGWK ( ([S
PIC32MX1XX/2XX /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ PP %RG\ >4)1@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS61168E-page 310 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A φ c β A2 A1 L L1 8QLWV 0,//,0(7(56 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± )RRW /HQ
PIC32MX1XX/2XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61168E-page 312 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX APPENDIX A: REVISION HISTORY This revision includes the addition of the following devices: Revision A (May 2011) • PIC32MX130F064B • PIC32MX230F064B This is the initial released version of this document.
PIC32MX1XX/2XX TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section 4.0 “Memory Organization” Update Description Added Memory Maps for the new devices (see Figure 4-3 and Figure 4-4). Removed the BMXCHEDMA bit from the Bus Matrix Register map (see Table 4-1). Added the REFOTRIM register, added the DIVSWEN bit to the REFOCON registers, added Note 4 to the ULOCK and SOSCEN bits and added the PBDIVRDY bit in the OSCCON register in the in the System Control Register map (see Table 4-16).
PIC32MX1XX/2XX TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section 29.0 “Electrical Characteristics” Update Description Updated the Absolute Maximum Ratings (removed Voltage on VCORE with respect to VSS). Added the SPDIP specification to the Thermal Packaging Characteristics (see Table 29-2). Updated the Typical values for parameters DC20-DC24 in the Operating Current (IDD) specification (see Table 29-5).
PIC32MX1XX/2XX Revision D (February 2012) All occurrences of VUSB were changed to: VUSB3V3. In addition, text and formatting changes were incorporated throughout the document. All other major changes are referenced by their respective section in Table A-3. TABLE A-3: MAJOR SECTION UPDATES Section Update Description “32-bit Microcontrollers (up to 128 Corrected a part number error in all pin diagrams.
PIC32MX1XX/2XX Revision E (October 2012) All singular pin diagram occurrences of CVREF were changed to: CVREFOUT. In addition, minor text and formatting changes were incorporated throughout the document. All major changes are referenced by their respective section in Table A-4. TABLE A-4: MAJOR SECTION UPDATES Section Update Description “32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog” Updated the following feature sections: 2.
PIC32MX1XX/2XX Notes: DS61168E-page 318 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX INDEX CPU Numerics 50 MHz Electrical Characteristics ..................................... 285 A AC Characteristics ............................................................ 253 10-Bit Conversion Rate Parameters ......................... 275 ADC Specifications ................................................... 273 Analog-to-Digital Conversion Requirements............. 276 EJTAG Timing Requirements ................................... 284 Internal FRC Accuracy.............................
PIC32MX1XX/2XX Memory Organization.......................................................... 35 Layout ......................................................................... 35 Microchip Internet Web Site .............................................. 323 MPLAB ASM30 Assembler, Linker, Librarian ................... 240 MPLAB Integrated Development Environment Software .. 239 MPLAB PM3 Device Programmer..................................... 242 MPLAB REAL ICE In-Circuit Emulator System.................
PIC32MX1XX/2XX U1IR (USB Interrupt)................................................. 126 U1OTGCON (USB OTG Control) ............................. 124 U1OTGIE (USB OTG Interrupt Enable) .................... 122 U1OTGIR (USB OTG Interrupt Status)..................... 121 U1OTGSTAT (USB OTG Status).............................. 123 U1PWRC (USB Power Control)................................ 125 U1SOF (USB SOF Threshold).................................. 136 U1STAT (USB Status) ..................................
PIC32MX1XX/2XX NOTES: DS61168E-page 322 Preliminary 2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC32MX1XX/2XX READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC32MX1XX/2XX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC32 MX 1XX F 032 D T - 50 I / PT - XXX Example: PIC32MX110F032DT-I/PT: General purpose PIC32, 32-bit RISC MCU with M4K® core, 32 KB program memory, 44-pin, Industrial temperature, TQFP package.
PIC32MX1XX/2XX NOTES: DS61168E-page 326 Preliminary 2011-2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.