Information

PIC32MX1XX/2XX
DS80000531E-page 6  2011-2013 Microchip Technology Inc.
9. Module: I/O Ports
Output High Voltage (VOH) on the RA0 and RA1
pins is not within the published data sheet
specification if the I2C1 module is enabled. In
addition, internal capacitance on these pins is one
and one-half (1.5) and two times higher,
respectively, than other I/O ports.
Work around
Disable slew rate control of the I2C1 module by
setting the DISSLW bit (I2C1CON<9>).
There is no workaround for higher capacitance.
Affected Silicon Revisions
10. Module: CPU
During normal operation, if a CPU write operation
is interrupted by an incoming interrupt, it should be
aborted (not completed) and resumed after the
interrupt is serviced. However, some of these write
operations may not be aborted, resulting in a
double write to peripherals by the CPU (the first
write during the interrupt and the second write after
the interrupt is serviced).
Work around
Most peripherals are not affected by this issue, as
a double write will not have a negative impact.
However, the following communication peripherals
will double-send data if their respective transmit
buffers are written twice: SPI, I
2
C, UART and PMP.
To avoid double transmission of data, utilize DMA
to transfer data to these peripherals or disable
interrupts while writing to these peripherals.
Affected Silicon Revisions
11. Module: Oscillator
A clock signal is present on the CLKO pin,
regardless of the clock source and setting of the
CLKO Enable Configuration bit, OSCIOFNC
(DEVCFG1<10>), during a Power-on Reset
(POR) condition.
Work around
Do not connect the CLKO pin to a device that
would be adversely affected by rapid pin toggling
or a frequency other than that defined by the
oscillator configuration. Do not use the CLKO pin
as an input if the device connected to the CLKO
pin would be adversely affected by the pin driving
a signal out.
Affected Silicon Revisions
12. Module: Input Capture
All input capture modes selectable by ICM<2:0>,
with the exception of Interrupt-only mode, will not
work when the CPU enters Idle or Sleep mode.
Work around
Configure the Input Capture module for Interrupt-
only mode (ICM<2:0> = 111) when the CPU is in
Sleep or Idle mode.
Affected Silicon Revisions
13. Module: Watchdog Timer (WDT)
When the Watchdog Timer module is used in
Windowed mode, the module may issue a reset
even if the user tries to clear the module within the
allowed window.
Work around
None.
Affected Silicon Revisions
Device Flash
Memory (KB)
Device Silicon Revision
A0 A1
16/32
XX
64/128
XX
Device Flash
Memory (KB)
Device Silicon Revision
A0 A1
16/32
XX
64/128
XX
Device Flash
Memory (KB)
Device Silicon Revision
A0 A1
16/32
XX
64/128
XX
Device Flash
Memory (KB)
Device Silicon Revision
A0 A1
16/32
XX
64/128
XX
Device Flash
Memory (KB)
Device Silicon Revision
A0 A1
16/32
XX
64/128
XX