Information

PIC32MX1XX/2XX
DS80000531E-page 4  2011-2013 Microchip Technology Inc.
Silicon Errata Issues
1. Module: Voltage Regulator
Device may not exit the Brown-out Reset (BOR)
state if a BOR event occurs.
Work arounds
Work around 1:
VDD must remain within the published specification
(see parameter DC10 of the device data sheet).
Work around 2:
Reset the device by providing the Power-on Reset
(POR) condition.
Affected Silicon Revisions
2. Module: Oscillator
If the Primary Oscillator (POSC) mode is
implemented and a Fail-Safe Clock Monitor
(FSCM) event occurs (failure of the external
primary clock), the internal clock source will switch
to the FRC oscillator. Subsequent firmware clock
switch requests from the FRC oscillator to other
clock sources will fail and the device will continue
to execute on the FRC oscillator. On repair of the
external clock source and a power-on state, the
device will resume operation with the primary
oscillator clock source.
Work around
None.
Affected Silicon Revisions
3. Module: I
2
C™
The slave address, 0x78, is one of a group of
reserved addresses. It is used as the upper byte of
a 10-bit address when 10-bit addressing is
enabled. The I
2
C module control register allows
the programmer to enable both 10-bit addressing
and strict enforcement of reserved addressing,
with the A10M and STRICT bits, respectively.
When both bits are cleared, the device should
respond to the reserved address 0x78, but it does
not.
Work around
None.
Affected Silicon Revisions
4. Module: USB
If the bus has been idle for more than 3 ms, the
UIDLE interrupt flag is set. If software clears the
interrupt flag and the bus remains idle, the UIDLE
interrupt flag will not be set again.
Work around
Software can leave the UIDLE bit set until it has
received some indication of bus resumption (i.e.,
Resume, Reset, SOF, or Error).
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. The table
provided in each issue indicates which
issues exist for a particular revision of
silicon based on memory size.
Device Flash
Memory (KB)
Device Silicon Revision
A0 A1
16/32 X
64/128 X
Device Flash
Memory (KB)
Device Silicon Revision
A0 A1
16/32 X X
64/128 X X
Device Flash
Memory (KB)
Device Silicon Revision
A0 A1
16/32 X X
64/128 X X
Note: Resume and Reset are the only interrupts
that should be following UIDLE assertion.
If the UIDLE bit is set, it should be okay to
suspend the USB module (as long as this
code is protected by the GUARD and/or
ACTPEND logic). This will require soft-
ware to clear the UIDLE interrupt enable
bit to exit the USB ISR (if using interrupt
driven code).
Device Flash
Memory (KB)
Device Silicon Revision
A0 A1
16/32 X X
64/128 X X