Information

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04
DS80000441J-page 8  2009-2013 Microchip Technology Inc.
16. Module: ECAN™
The WAKIF bit in the CiINTF register cannot be
cleared by software instruction after device is inter-
rupted from Sleep due to activity on the CAN bus.
When the device wakes up from Sleep due to CAN
bus activity, the ECAN module is placed in
operational mode. The ECAN event interrupt occurs
due to the WAKIF flag. Trying to clear the flag in the
Interrupt Service Routine (ISR) may not clear the
flag. The WAKIF bit being set will not cause
repetitive Interrupt Service Routine execution.
Work around
Although the WAKIF bit does not clear, the device,
Sleep and ECAN wake function continues to work
as expected. If the ECAN event is enabled, the
CPU will enter the Interrupt Service Routine due to
the WAKIF flag getting set. The application can
maintain a secondary flag, which tracks the device
Sleep and wake events.
Affected Silicon Revisions
17. Module: ECAN
The ECAN module may not store received data in
the correct location. When this occurs, the receive
buffers will become corrupted. In addition, it is also
possible for the transmit buffers to become
corrupted. This issue is more likely to occur as the
CAN bus speed approaches 1 Mbps.
Work around
Do not use the DMA with ECAN in Peripheral
Indirect mode. Use the DMA in Register Indirect
mode, Continuous mode enabled and Ping Pong
mode disabled. The receive DMA channel count
should be set to 8 words. The transmit DMA
channel count should be set for the actual message
size (maximum of 7 words for Extended CAN
messages and 6 words for Standard CAN
Messages). To simplify application error handling
while using this mode, only one TX buffer should be
used. While message filtering is not affected,
messages will not be stored at distinct RX buffers.
Instead, all messages are stored contiguously in
memory. The start of this memory is pointed to by
the receive DMA channel. The application must still
clear RXFULx flags and other interrupt flags. The
application must manage the RX buffer memory.
Affected Silicon Revisions
18. Module: CPU
The EXCH instruction does not execute correctly.
Work around
If writing source code in assembly, the
recommended work around is to replace:
EXCH Wsource, Wdestination
with:
PUSH Wdestination
MOV Wsource, Wdestination
POP Wsource
If using the MPLAB C30 C compiler, specify the
compiler option: -merrata=exch (Project > Build
Options > Projects > MPLAB C30 > Use Alternate
Settings).
Affected Silicon Revisions
19. Module: SPI
Writing to the SPIxBUF register, as soon as the
TBF bit is cleared, will cause the SPIx module to
ignore the written data. Applications which use SPI
with DMA will not be affected by this erratum.
Work around
After the TBF bit is cleared, wait for a minimum
duration of one SPI clock before writing to the
SPIxBUF register.
Alternatively, do one of the following:
• Poll the RBF bit and wait for it to get set before
writing to the SPIxBUF register
• Poll the SPI interrupt flag and wait for it to get
set before writing to the SPIxBUF register
• Use an SPI Interrupt Service Routine
•Use DMA
Affected Silicon Revisions
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