Information
2009-2013 Microchip Technology Inc. DS80000441J-page 7
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04
11. Module: UART
The UARTx error interrupt may not occur, or may
occur at an incorrect time, if multiple errors occur
during a short period of time.
Work around
Read the error flags in the UxSTA register
whenever a byte is received to verify the error
status. In most cases, these bits will be correct,
even if the UARTx error interrupt fails to occur.
Affected Silicon Revisions
12. Module: UART
When the UARTx is operating in 8-bit mode
(PDSEL<1:0> = 0x) and using the IrDA encoder/
decoder (IREN = 1), the module incorrectly
transmits a data payload of 80h as 00h.
Work around
None.
Affected Silicon Revisions
13. Module: Comparator
If CxOUTEN (CMCON) is set and the Comparator
Enable bit, CxEN (CMCON) is disabled, the
remappable Comparator Output pins, C1OUT and
C2OUT, cannot be used as general purpose I/O
pins.
Work around
When the comparator module is disabled the
CxOUTEN bit should be reset so that the
remappable Comparator Output pins, C1OUT and
C2OUT, are not driven onto the output pad.
Affected Silicon Revisions
14. Module: Internal Voltage Regulator
When the VREGS bit (RCON<8>) is set to a logic
‘0’, the device may reset and higher Sleep current
may be observed.
Work around
Ensure the VREGS bit (RCON<8>) is set to a logic
‘1’ for device Sleep mode operation.
Affected Silicon Revisions
15. Module: PSV Operations
An address error trap occurs in certain addressing
modes when accessing the first four bytes of a
PSV page. This only occurs when using the
following addressing modes:
• MOV.D
• Register Indirect Addressing (Word or Byte
mode) with Pre/Post-Decrement
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB C30,
Version 3.11 or higher, provides the following
command-line switch that implements a work
around for the erratum.
-merrata=psv_trap
Refer to the readme.txt file in the MPLAB C30
v3.11 toolsuite for further details.
Affected Silicon Revisions
A1 A2 A3 A4 A5
XXXX
X
A1 A2 A3 A4 A5
XXXX
X
A1 A2 A3 A4
A5
XXXX
X
A1 A2 A3 A4 A5
XXXX
X
A1 A2 A3 A4
A5
XXXX
X