Information

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04
DS80000441J-page 4  2009-2013 Microchip Technology Inc.
CPU Interrupt
Disable
26. When a previous DISI instruction is active (i.e., the
DISICNT register is non-zero), and the value of the
DISICNT register is updated manually, the DISICNT
register freezes and disables interrupts permanently.
XXXXX
CPU div.sd 27. When using the div.sd instruction, the Overflow bit
is not getting set when an overflow occurs.
XXXXX
UART TX Interrupt 28. A Transmit (TX) interrupt may occur before the data
transmission is complete.
XXXXX
JTAG Flash
Programming
29. JTAG Flash programming is not supported. X X X X X
TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature
Item
Number
Issue Summary
Affected
Revisions
(1)
A1 A2 A3 A4 A5
Note 1: Only those issues indicated in the last column apply to the current silicon revision.