Information

 2009-2013 Microchip Technology Inc. DS80000441J-page 3
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04
UART Interrupts 11. The UART error interrupt may not occur, or may
occur at an incorrect time, if multiple errors occur
during a short period of time.
XXXXX
UART IR Mode 12. When the UARTx module is operating in 8-bit mode
(PDSEL<1:0> = 0x) and using the IrDA
®
encoder/
decoder (IREN = 1), the module incorrectly transmits
a data payload of 80h as 00h.
XXXXX
Comparator Output Pin 13. When CxOUTEN (CMCON) is set, the comparator
output pin cannot be used as a general purpose I/O
pin even if the comparator is disabled.
XXXXX
Internal
Voltage
Regulator
Sleep Mode 14. When the VREGS bit (RCON<8>) is set to a logic ‘0’,
the device may reset and higher Sleep current may
be observed.
XXXXX
PSV
Operations
— 15. An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
XXXXX
ECAN™ Sleep Mode 16. The WAKIF bit in the CiINTF register cannot be
cleared by a software instruction after the device is
interrupted from Sleep due to activity on the CAN
bus.
XXXXX
ECAN Receive
Operation
17. The ECAN module may not store the received data
in the correct location.
XXX
CPU EXCH
Instruction
18. The EXCH instruction does not execute correctly. X X X X X
SPI Transmit
Operation
19. Writing to the SPIxBUF register as soon as the TBF
bit is cleared will cause the SPIx module to ignore
written data.
XXXXX
UART Break
Character
Generation
20. The UARTx module will not generate back-to-back
Break characters.
XXXXX
ADC Current
Consumption
in Sleep
Mode
21. If the ADC module is in an enabled state when the
device enters Sleep mode, the Power-Down (I
PD)
current of the device may exceed the device data
sheet specifications.
XXXXX
RTCC Boundary
Scan
22. On 28-pin devices, JTAG boundary scan does not
function correctly for Pin 7. Both Pins 6 and 7 respond
to stimulus applied to Pin 7.
XXXXX
JTAG Operation
During Reset
23. The RTCC module gets reset on any device Reset,
instead of getting reset only on a POR or BOR.
XXXXX
All 150°C
Operation
24. These revisions of silicon only support 140°C
operation instead of 150°C for high-temperature
operating temperature.
XXX
I/O Port Data
Direction
Setting
25. When the RB8 pin is in open-drain configuration, the
data direction depends upon the TRISB9 bit instead
of the TRISB8 bit.
XXXXX
TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature
Item
Number
Issue Summary
Affected
Revisions
(1)
A1 A2 A3 A4 A5
Note 1: Only those issues indicated in the last column apply to the current silicon revision.