Information

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04
DS80000441J-page 2  2009-2013 Microchip Technology Inc.
PIC24HJ128GP202 0x0665
0x3001 0x3002 0x3002 0x3003 0x3004
PIC24HJ128GP204 0x0667
PIC24HJ128GP502 0x067D
PIC24HJ128GP504 0x067F
TABLE 1: SILICON DEVREV VALUES (CONTINUED)
Part Number Device ID
(1)
Revision ID for Silicon Revision
(2)
A1 A2 A3 A4 A5
Note 1: The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in
program memory.
2: Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) for detailed information on
Device and Revision IDs for your specific device.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature
Item
Number
Issue Summary
Affected
Revisions
(1)
A1 A2 A3 A4 A5
UART IR Mode 1. The 16x baud clock signal on the BCLK pin is
present only when the module is transmitting.
XXXXX
UART High-Speed
Mode
2. When the UARTx is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
XXXXX
SPI Transmit
Operation
3. The SPIx Transmit Buffer Full (SPITBF) flag does not
get set immediately after writing to the buffer.
XXXXX
SPI Frame Mode 4. The SPIx module will generate incorrect frame
synchronization pulses in Frame Master mode if
FRMDLY = 1.
XXXXX
I
2
C™ SFR Writes 5. The BCL bit in I2CxSTAT can only be cleared with
word instructions, and can be corrupted with byte
instructions and bit operations.
XXXXX
I
2
C 10-Bit
Addressing
6. When the I
2
C module is configured for 10-bit
addressing using the same Address bits (A10 and
A9) as other I
2
C devices, A10 and A9 bits may not
work as expected.
XXXXX
I
2
C 10-Bit
Addressing
7. When the I
2
C module is configured as a 10-bit slave
with an address of 0x02, the I2CxRCV register
content for the lower address byte is 0x01 rather than
0x02.
XXXXX
I
2
C — 8. With the I
2
C module enabled, the PORT bits and
external interrupt input functions (if any), associated
with SCLx and SDAx pins, will not reflect the actual
digital logic levels on the pins.
XXXXX
I
2
C 10-Bit
Addressing
9. The 10-bit slave does not set the RBF flag or load the
I2CxRCV register on address match if the Least Sig-
nificant bits (LSbs) of the address are the same as
the 7-bit reserved addresses.
XXXXX
I
2
C — 10. After the ACKSTAT bit is set when receiving a NACK,
it may be cleared by the reception of a Start or Stop
bit.
XXXXX
Note 1: Only those issues indicated in the last column apply to the current silicon revision.