Information

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04
DS80000441J-page 10  2009-2013 Microchip Technology Inc.
24. Module: All
The affected silicon revisions listed below are not
warranted for operation at +150°C.
Work around
Only use the affected revisions of silicon for high-
temperature operating range, from -40°C to
+140°C.
Affected Silicon Revisions
25. Module: I/O Port
When the ODCB8 bit is set to ‘1’ (open-drain con-
figuration), the data direction on the RB8 pin is
controlled by the TRISB9 bit instead of the TRISB8
bit.
Work around
Do not use the RB8 pin in open-drain configuration
while simultaneously using the RB9 pin.
Affected Silicon Revisions
26. Module: CPU
When a previous DISI instruction is active (i.e.,
the DISICNT register is non-zero), and the value of
the DISICNT register is updated manually, the
DISICNT register freezes and disables interrupts
permanently.
Work around
Avoid updating the DISICNT register manually.
Instead, use the DISI #n instruction with the
required value for ‘n’.
Affected Silicon Revisions
27. Module: CPU
When using the Signed 32-bit by 16-bit Division
instruction, div.sd, the Overflow bit does not
always get set when an overflow occurs.
Work around
Test for and handle overflow conditions outside of
the div.sd instruction.
Affected Silicon Revisions
28. Module: UART
When using UTXISEL<1:0> = 01 (interrupt when
last character is shifted out of the Transmit Shift
Register) and the final character is being shifted
out through the Transmit Shift Register, the
Transmit (TX) interrupt may occur before the final
bit is shifted out.
Work around
If it is critical that the interrupt processing occur
only when all transmit operations are complete,
hold off the interrupt routine processing by adding
a loop at the beginning of the routine that polls the
Transmit Shift Register Empty bit (TRMT) before
processing the rest of the interrupt.
Affected Silicon Revisions
29. Module: JTAG
JTAG Flash programming is not supported.
Work around
None.
Affected Silicon Revisions
A1 A2 A3 A4 A5
XXX
A1 A2 A3 A4 A5
XXXX
X
A1 A2 A3 A4
A5
XXXX
X
A1 A2 A3 A4 A5
XXXX
X
A1 A2 A3 A4
A5
XXXX
X
A1 A2 A3 A4 A5
XXXX
X