Datasheet

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
DS70293G-page 18 © 2007-2012 Microchip Technology Inc.
3.3 Special MCU Features
The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04
and PIC24HJ128GPX02/X04 features a 17-bit by 17-
bit, single-cycle multiplier. The multiplier can perform
signed, unsigned and mixed-sign multiplication. Using
a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication makes mixed-sign multiplication
possible.
The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04
and PIC24HJ128GPX02/X04 devices support 16/16
and 32/16 integer divide operations. All divide
instructions are iterative operations. They must be
executed within a REPEAT loop, resulting in a total
execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
A multi-bit data shifter is used to perform up to a 16-bit,
left or right shift in a single cycle.
FIGURE 3-1: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 CPU
CORE BLOCK DIAGRAM
Instruction
Decode and
Control
PCH PCL
Program Counter
16-bit ALU
24
23
Instruction Reg
PCU
16 x 16
W Register Array
ROM Latch
EA MUX
Interrupt
Controller
Stack
Control
Logic
Loop
Control
Logic
Control Signals
to Various Blocks
Literal Data
16
16
16
To Peripheral Modules
Data Latch
Address
Latch
16
X RAM
Address Generator Units
X Data Bus
DMA
Controller
DMA
RAM
17 x 17 Multiplier
Divide Support
16
16
23
23
16
8
PSV and Table
Data Access
Control Block
16
16
16
Program Memory
Data Latch
Address Latch