Information

© 2009-2011 Microchip Technology Inc. DS80467G-page 7
PIC24HJ32GP202/204 and PIC24HJ16GP304
19. Module: I
2
C
When the I
2
C module is operating in either Master
or Slave mode, after the ACKSTAT bit is set when
receiving a NACK, it may be cleared by the
reception of a Start or Stop bit.
Work around
Store the value of the ACKSTAT bit immediately
after receiving a NACK.
Affected Silicon Revisions
20. Module: CPU
The EXCH instruction does not execute correctly.
Work around
If writing source code in assembly, the
recommended work around is to replace:
EXCH Wsource, Wdestination
with:
PUSH Wdestination
MOV Wsource, Wdestination
POP Wsource
If using the MPLAB C30 C compiler, specify the
compiler option: -merrata=exch (Project > Build
Options > Projects > MPLAB C30 > Use Alternate
Settings).
Affected Silicon Revisions
21. Module: PGEC3/PGED3 Programming
Pins
When using the PGEC3/PGED3 pins for device
programming, the programming time may be
slower as compared to other available PGECx/
PGEDx pin pairs, because the Enhanced ICSP
programming algorithm cannot be executed on
this pin pair.
Refer to the “dsPIC33F/PIC24H Flash
Programming Specification” (DS70152) for
additional information on this limitation.
Work around
Use alternate PGECx/PGEDx programming pin
pairs.
Affected Silicon Revisions
22. Module: UART
The UART module will not generate consecutive
break characters. Trying to perform a back-to-back
Break character transmission will cause the UART
module to transmit the dummy character used to
generate the first Break character instead of
transmitting the second Break character. Break
characters are generated correctly if they are
followed by non-Break character transmission.
Work around
None.
Affected Silicon Revisions
A2 A3 A4 A5 A6
XXXX
X
A2 A3 A4 A5
A6
XXXX
X
A2 A3 A4 A5 A6
XXXX
X
A2 A3 A4 A5
A6
XXXXX