Information

PIC24HJ32GP202/204 and PIC24HJ16GP304
DS80467G-page 4 © 2009-2011 Microchip Technology Inc.
Silicon Errata Issues
1. Module: JTAG
JTAG programming does not work.
Work around
None.
Affected Silicon Revisions
2. Module: UART
The auto-baud feature may not calculate the correct
baud rate when the High Baud Rate Enable bit,
BRGH, is set. With the BRGH bit set, the baud rate
calculation used is the same as BRG = 0.
Work around
If the auto-baud feature is needed, use the Low
Baud Rate mode by clearing the BRGH bit.
Affected Silicon Revisions
3. Module: UART
With the auto-baud feature selected, the Sync
Break character (0x55) may be loaded into the
FIFO as data.
Work around
To prevent the Sync Break character from being
loaded into the FIFO, load the UxBRG register with
either 0x0000 or 0xFFFF prior to enabling the
auto-baud feature (ABAUD = 1).
Affected Silicon Revisions
4. Module: UART
The auto-baud feature may miscalculate for
certain baud rate and clock speed combinations,
resulting in a BRG value that is greater than or less
than the expected value by 1. This may result in
reception or transmission failures.
Work around
Test the auto-baud rate at various clock speed and
baud rate combinations that would be used in an
application. If an inaccurate BRG value is
generated, manually correct the baud rate in user
software.
Affected Silicon Revisions
5. Module: UART
When an auto-baud is detected, the receive
interrupt may occur twice. The first interrupt occurs
at the beginning of the Start bit and the second
after reception of the Sync field character.
Work around
If an extra interrupt is detected, ignore the
additional interrupt.
Affected Silicon Revisions
6. Module: UART
When the UART is configured for IR interface
operations (UxMODE<9:8> = 11), the 16x baud
clock signal on the BCLK pin is present only when
the module is transmitting. The pin is idle at all
other times.
Work around
Configure one of the output compare modules to
generate the required baud clock signal when the
UART is receiving data or in an Idle state.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A6).
A2 A3 A4 A5
A6
XXXXX
A2 A3 A4 A5 A6
XXXXX
A2 A3 A4 A5 A6
XXXXX
A2 A3 A4 A5 A6
XXXXX
A2 A3 A4 A5 A6
XXXX
X
A2 A3 A4 A5
A6
XXXX
X