Information

© 2009-2011 Microchip Technology Inc. DS80467G-page 3
PIC24HJ32GP202/204 and PIC24HJ16GP304
I
2
C — 17. With the I
2
C module enabled, the PORT bits and
external Interrupt Input functions (if any) associated
with SCL and SDA pins will not reflect the actual
digital logic levels on the pins.
XXXXX
I
2
C 10-bit
Addressing
18. The 10-bit slave does not set the RBF flag or load
the I2CxRCV register, on address match if the
Least Significant bits (LSbs) of the address are the
same as the 7-bit reserved addresses.
XXXXX
I
2
C — 19. After the ACKSTAT bit is set when receiving a
NACK, it may be cleared by the reception of a Start
or Stop bit.
XXXXX
CPU EXCH
Instruction
20. The EXCH instruction does not execute correctly. X X X X X
PGEC3/
PGED3
Programming
Pins
Device
Programming
21. When using the PGEC3/PGED3 pins for device
programming, the programming time may be
slower as compared to other available PGECx/
PGEDx pin pairs.
XXXXX
UART Break
Character
Generation
22. The UART module will not generate back-to-back
Break characters.
XXXXX
ADC Current
Consumption
in Sleep
Mode
23. If the ADC module is in an enabled state when the
device enters Sleep mode, the power-down
current (I
PD) of the device may exceed the device
data sheet specifications.
XXXXX
All 150ºC
Operation
24. These revisions of silicon only support 140ºC
operation instead of 150ºC for Hi-Temp operating
temperature.
XXXX
CPU Interrupt
Disable
25. When a previous DISI instruction is active (i.e.,
the DISICNT register is non-zero), and the value of
the DISICNT register is updated manually, the
DISICNT register freezes and disables interrupts
permanently.
XXXXX
CPU div.sd 26. When using the div.sd instruction, the overflow
bit is not getting set when an overflow occurs.
XXXXX
UART TX Interrupt 27. A transmit (TX) Interrupt may occur before the data
transmission is complete.
XXXXX
JTAG Flash
Programming
28. JTAG Flash programming is not supported. X X X X X
TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature
Item
Number
Issue Summary
Affected Revisions
(1)
A2 A3 A4 A5 A6
Note 1: Only those issues indicated in the last column apply to the current silicon revision.