Information

PIC24HJ32GP202/204 and PIC24HJ16GP304
DS80467G-page 2 © 2009-2011 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature
Item
Number
Issue Summary
Affected Revisions
(1)
A2 A3 A4 A5 A6
JTAG Flash
Programming
1. JTAG programming does not work. X X X X X
UART High-Speed
Mode
2. The auto-baud feature may not calculate the cor-
rect baud rate when the Baud Rate Generator
(BRG) is set up for 4x mode.
XXXXX
UART Auto-Baud 3. With the auto-baud feature selected, the Sync
Break character (0x55) may be loaded into the
FIFO as data.
XXXXX
UART Auto-Baud 4. The auto-baud feature measures baud rate inaccu-
rately for certain baud rate and clock speed combi-
nations.
XXXXX
UART Auto-Baud 5. When an auto-baud is detected, the receive inter-
rupt may occur twice.
XXXXX
UART IR Mode 6. The 16x baud clock signal on the BCLK pin is pres-
ent only when the module is transmitting.
XXXXX
UART High-Speed
Mode
7. When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
XXXXX
SPI SCKx Pins 8. The SPIxCON1 DISSCK bit does not influence port
functionality.
XXXXX
I
2
C™SFR Writes9. The BCL bit in I2CSTAT can be cleared only with
16-bit operation and can be corrupted with 1-bit or
8-bit operations on I2CSTAT.
XXXXX
I
2
C 10-bit
Addressing
10. When the I
2
C module is configured for 10-bit
addressing using the same address bits (A10 and
A9) as other I
2
C device A10 and A9 bits may not
work as expected.
XXXXX
Product
Identification
Extended
Temperature
11. Revision A2 devices marked as extended temper-
ature range (E) devices, support only industrial
temperature range (I).
X
UART Interrupts 12. The UART error interrupt may not occur, or may
occur at an incorrect time, if multiple errors occur
during a short period of time.
XXXXX
UART IR Mode 13. When the UART module is operating in 8-bit mode
(PDSEL = 0x) and using the IrDA
®
encoder/
decoder (IREN = 1), the module incorrectly trans-
mits a data payload of 80h as 00h.
XXXXX
Internal
Voltage
Regulator
Sleep Mode 14. When the VREGS bit (RCON<8>) is set to a logic
‘0’, device may Reset and higher sleep current
may be observed.
XXXXX
PSV
Operations
— 15. An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
XXXXX
I
2
C 10-bit
Addressing
16. When the I
2
C module is configured as a 10-bit
slave with and address of 0x02, the I2CxRCV reg-
ister content for the lower address byte is 0x01
rather than 0x02.
XXXXX
Note 1: Only those issues indicated in the last column apply to the current silicon revision.