Datasheet

© 2007-2011 Microchip Technology Inc. DS70289J-page 283
PIC24HJ32GP202/204 AND PIC24HJ16GP304
Illegal Opcode ....................................................... 53, 61
Trap Conflict.......................................................... 60, 61
Uninitialized W Register........................................ 53, 61
Reset Sequence ................................................................. 63
Resets................................................................................. 53
S
Serial Peripheral Interface (SPI) ....................................... 145
Software Reset Instruction (SWR) ...................................... 60
Software Simulator (MPLAB SIM)..................................... 197
Software Stack Pointer, Frame Pointer
CALL Stack Frame...................................................... 40
Special Features of the CPU ............................................ 179
SPI Module
SPI1 Register Map...................................................... 33
Symbols Used in Opcode Descriptions............................. 188
System Control
Register Map............................................................... 39
T
Temperature and Voltage Specifications
AC ..................................................................... 211, 247
Timer1............................................................................... 127
Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ..................... 131
Timing Characteristics
CLKO and I/O ........................................................... 214
Timing Diagrams
10-bit A/D Conversion............................................... 241
10-bit A/D Conversion (CHPS<1:0> = 01, SIMSAM = 0,
ASAM = 0, SSRC<2:0> = 000) ......................... 241
12-bit A/D Conversion
(ASAM = 0, SSRC<2:0> = 000)........................ 240
Brown-out Situations................................................... 60
External Clock........................................................... 212
I2Cx Bus Data (Master Mode) .................................. 233
I2Cx Bus Data (Slave Mode) .................................... 235
I2Cx Bus Start/Stop Bits (Master Mode) ................... 233
I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 235
Input Capture (CAPx)................................................ 219
OC/PWM................................................................... 220
Output Compare (OCx)............................................. 219
Reset, Watchdog Timer, Oscillator Start-up Timer
and Power-up Timer ......................................... 215
Timer1, 2, 3, 4, 5, 6, 7, 8, 9 External Clock .............. 217
Timing Requirements
ADC Conversion (10-bit mode) ................................ 252
ADC Conversion (12-bit Mode) ................................ 252
CLKO and I/O ........................................................... 214
External Clock .......................................................... 212
Input Capture............................................................ 219
SPIx Master Mode (CKE = 0) ................................... 248
SPIx Module Master Mode (CKE = 1) ...................... 248
SPIx Module Slave Mode (CKE = 0) ........................ 249
SPIx Module Slave Mode (CKE = 1) ........................ 249
Timing Specifications
10-bit A/D Conversion Requirements ....................... 242
12-bit A/D Conversion Requirements ....................... 240
I2Cx Bus Data Requirements (Master Mode)........... 234
I2Cx Bus Data Requirements (Slave Mode)............. 236
Output Compare Requirements................................ 219
PLL Clock ......................................................... 213, 247
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out
Reset Requirements......................................... 216
Simple OC/PWM Mode Requirements ..................... 220
Timer1 External Clock Requirements....................... 217
Timer2 External Clock Requirements....................... 218
Timer3 External Clock Requirements....................... 218
U
UART Module
UART1 Register Map ................................................. 33
Using the RCON Status Bits............................................... 61
V
Voltage Regulator (On-Chip) ............................................ 183
W
Watchdog Time-out Reset (WDTR).................................... 60
Watchdog Timer (WDT)............................................ 179, 184
Programming Considerations ................................... 184
WWW Address ................................................................. 283
WWW, On-Line Support ....................................................... 6