Datasheet

PIC24HJ32GP202/204 AND PIC24HJ16GP304
DS70289J-page 272 © 2007-2011 Microchip Technology Inc.
Section 15.0 “Inter-Integrated
Circuit (I
2
C™)”
Removed the following sections, which are now available in the related
section of the dsPIC33F/PIC24H Family Reference Manual:
• 15.3 “I
2
C Interrupts”
• 15.4 “Baud Rate Generator” (retained Figure 15-1: I
2
C Block Diagram)
• 15.5 “I
2
C Module Addresses”
• 15.6 “Slave Address Masking”
• 15.7 “IPMI Support”
• 15.8 “General Call Address Support”
• 15.9 “Automatic Clock Stretch”
• 15.10 “Software Controlled Clock Stretching (STREN = 1)”
• 15.11 “Slope Control”
• 15.12 “Clock Arbitration”
• 15.13 “Multi-Master Communication, Bus Collision, and Bus Arbitration”
• 15.14 “Peripheral Pin Select Limitations”
Section 16.0 “Universal
Asynchronous Receiver Transmitter
(UART)”
Removed the following sections, which are now available in the related
section of the dsPIC33F/PIC24H Family Reference Manual:
• 16.1 “UART Baud Rate Generator”
• 16.2 “Transmitting in 8-bit Data Mode”
• 16.3 “Transmitting in 9-bit Data Mode”
• 16.4 “Break and Sync Transmit Sequence”
• 16.5 “Receiving in 8-bit or 9-bit Data Mode”
• 16.6 “Flow Control Using UxCTS
and UxRTS Pins”
• 16.7 “Infrared Support”
Removed IrDA references and Note 1, and updated the bit and bit value
descriptions for UTXINV (UxSTA<14>) in the UARTx Status and Control
Register (see Register 16-2).
Section 17.0 “10-bit/12-bit Analog-
to-Digital Converter (ADC)”
Removed Equation 17-1: ADC Conversion Clock Period and Figure 17-2:
ADC Transfer Function (10-bit Example).
Added ADC1 Module Block Diagram for PIC24HFJ16GP304 and
PIC24HJ32GP204 Devices (Figure 17-1) and ADC1 Module Block Diagram
FOR PIC24HJ32GP202 Devices (Figure 17-2).
Added Note 2 to Figure 17-3: ADC Conversion Clock Period Block Diagram.
Added device-specific information to Note 1 in the ADC1 Input Scan Select
Register Low (see Register 17-6), and updated the default bit value for bits
12-10 (CSS12-CSS10) from U-0 to R/W-0.
Added device-specific information to Note 1 in the ADC1 Port Configuration
Register Low (see Register 17-7), and updated the default bit value for bits
12-10 (PCFG12-PCFG10) from U-0 to R/W-0.
TABLE 25-1: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description