Datasheet

© 2008 Microchip Technology Inc. DS80280G-page 3
PIC24HJXXXGPX06/X08/X10
38. DMA
NULL Data Peripheral Write mode for the DMA
channel does not function.
39. DMA
DMA request Fault condition does not generate a
DMA error trap.
40. DMA
DMA channel writes an additional NULL value to
the peripheral register.
41. REPEAT Instruction
Any instruction executed inside a REPEAT loop
that produces a Read-After-Write stall condition,
results in the instruction being executed fewer
times than was intended.
42. FRC Oscillator
For certain values of the TUN<5:0> bits
(OSCTUN<5:0>), the resultant frequencies are
incorrect.
43. UART Module
The 16x baud clock signal on the BCLK pin is
present only when the module is transmitting.
44. SPI Module
The SPIxCON1 DISSCK bit does not influence
port functionality.
45. I
2
C Module
The BCL bit in I2CSTAT can be cleared only with
16-bit operation and can be corrupted with 1-bit or
8-bit operations on I2CSTAT.
46. I
2
C Module: 10-bit addressing mode
When the I
2
C module is configured for 10-bit
addressing using the same address bits (A10 and
A9) as other I
2
C devices, the A10 and A9 bits may
not work as expected.
47. I
2
C Module: 10-bit Addressing Mode
When the I
2
C module is configured as a 10-bit
slave with an address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather than 0x02.
48. I
2
C Module
With the I
2
C module enabled, the PORT bits and
external Interrupt Input functions (if any)
associated with SCL and SDA pins will not reflect
the actual digital logic levels on the pins.
49. I
2
C Module: 10-bit Addressing Mode
The 10-bit slave does not set the RBF flag or load
the I2CxRCV register on address match if the
Least Significant bits of the address are the same
as the 7-bit reserved addresses.
50. Internal Voltage Regulator
When the VREGS (RCON<8>) bit is set to a logic
‘0’, higher sleep current may be observed.
51. ECAN Module
The ECAN module does not generate a CAN
event interrupt when coming out of Disable mode
on bus wake-up activity even if the WAKIE bit in
the CiINTE register is set.
52. PSV Operations
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
53. UART (UxE Interrupt)
The UART error interrupt may not occur, or may
occur at an incorrect time, if multiple errors occur
during a short period of time.
54. UART Module
When the UART module is operating in 8-bit mode
(PDSEL = 0x) and using the IrDA
®
encoder/decoder (IREN = 1), the module
incorrectly transmits a data payload of 80h as 00h.
The following sections describe the errata and work
around to these errata, where they may apply.