Datasheet

PIC24HJXXXGPX06/X08/X10
DS80280G-page 2 © 2008 Microchip Technology Inc.
10. ECAN™ Module
ECAN transmissions may be incorrect if multiple
transmit buffers are simultaneously queued for
transmission.
11. ECAN Module
Under specific conditions, the first five bits of a
transmitted identifier may not match the value in
the transmit buffer ID register.
12. ECAN Module Loopback Mode
The ECAN module (ECAN1 or ECAN2) does not
function correctly in Loopback mode.
13. I
2
C™ Module
The Bus Collision Status bit does not get set when
a bus collision occurs during a Restart or Stop
event.
14. INT0, ADC and Sleep/Idle Mode
ADC event triggers from the INT0 pin will not
wake-up the device from Sleep or Idle mode if the
SMPI bits are non-zero.
15. Doze Mode and Traps
The address error trap, stack error trap, math error
trap and DMA error trap will not wake-up a device
from Doze mode.
16. JTAG Programming
JTAG programming does not work.
17. UART
With the parity option enabled, a parity error may
occur if the Baud Rate Generator (BRG) contains
an odd value.
18. UART
The Receive Buffer Overrun Error Status bit may
get set before the UART FIFO has overflowed.
19. UART
UART receptions may be corrupted if the BRG is
set up for 4x mode.
20. UART
The UTXISEL0 bit is always read back as zero.
21. UART
The auto-baud feature may not calculate the
correct baud rate when the BRG is set up for 4x
mode.
22. UART
With the auto-baud feature selected, the sync
break character (0x55) may be loaded into the
FIFO as data.
23. I
2
C Module
A write collision does not prevent the transmit
register from being written.
24. I
2
C Module
The ACKSTAT bit only reflects the received
ACK/NACK status for Master transmissions, but
not for Slave transmissions.
25. I
2
C Module
The D_A Status bit does not get set on a slave
write to the transmit register.
26. Traps and Idle Mode
If a clock failure occurs when the device is in Idle
mode, the oscillator failure trap does not vector to
the Trap Service Routine (TSR).
27. MCLR
Wake-up from Sleep Mode
An MCLR
wake-up from Sleep mode does not wait
for the on-chip voltage regulator to power-up.
28. ECAN Module
The C1RXOVF2 and C2RXOVF2 registers always
read back as 0x0000.
29. FRC Oscillator
Internal FRC accuracy parameters are not within
the published data sheet specifications.
30. SPI Module
SPI1 functionality for pin 34 (U1RX/SDI1/RF2) is
erroneously enabled by the SPI2 module.
31. UART
The auto-baud feature measures baud rate inac-
curately for certain baud rate and clock speed
combinations.
32. Device ID Register
The content of the Device ID register changes
from the factory programmed value.
33. DMA Module
DMA data transfers that are active in Single-Shot
mode while the device is in Sleep or Idle mode
may result in more data transfers than expected.
34. Doze Mode and Traps
A DMA error trap may not be generated when the
device is in Doze mode.
35. Output Compare Module
In Dual Compare Match mode, the OCx output is
not reset when the OCxR and OCxRS registers
are loaded with values having a difference of 1.
36. UART
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
37. UART
When an auto-baud is detected, the receive
interrupt may occur twice.