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PIC24HJXXXGPX06/X08/X10

The PIC24H (Rev. A2/A3/A4) devices you received

were found to conform to the specifications and func-

tionality described in the following documents:

• DS70175 – “PIC24H Family Data Sheet”

• DS70157 – “dsPIC30F/33F Programmer’s

Reference Manual”

• DS70046 – “dsPIC30F Family Reference Manual”

The exceptions to the specifications in the documents

listed above are described in this section. The specific

devices for which these exceptions are described are

listed below:

• PIC24HJ64GP206

• PIC24HJ64GP210

• PIC24HJ64GP506

• PIC24HJ64GP510

• PIC24HJ128GP206

• PIC24HJ128GP210

• PIC24HJ128GP306

• PIC24HJ128GP310

• PIC24HJ128GP506

• PIC24HJ128GP510

• PIC24HJ256GP206

• PIC24HJ256GP210

• PIC24HJ256GP610

PIC24H Rev. A2/A3/A4 silicon is identified by

performing a “Reset and Connect” operation to the

device using MPLAB

ICD 2 with MPLAB IDE v7.40 or

later. The output window will show a successful

connection to the device specified in Configure>Select

Device. The resulting DEVREV register values for Rev.

A2/A3/A4 silicon are 0x3002, 0x3004, and 0x3040,

respectively.

The errata described in this document will be

addressed in future revisions of silicon.

Silicon Errata Summary

The following list summarizes the errata described in

further detail through the remainder of this document:

1. Doze Mode

When Doze mode is enabled, any writes to a

peripheral SFR can cause other updates to that

current CPU clock cycle.

2. 12-bit Analog-to-Digital Converter (ADC)

Module

For this revision of silicon, the 12-bit ADC module

INL, DNL and signal acquisition time parameters

are not within the published data sheet

specifications.

3. 10-bit ADC Module

For this revision of silicon, the 10-bit ADC module

DNL, conversion speed and signal acquisition time

parameters are not within the published data sheet

specifications.

4. DMA Module: Interaction with EXCH Instruction

The EXCH instruction does not execute correctly

when one of the operands contains a value equal

to the address of the DMAC SFRs.

5. DISI Instruction

The DISI instruction will not disable interrupts if a

DISI instruction is executed in the same

instruction cycle that the DISI counter

decrements to zero.

6. Output Compare Module in PWM Mode

The output compare module will miss one

compare event when the duty cycle register value

is updated from 0x0000 to 0x0001.

7. SPI Module in Frame Master Mode

The SPI module will fail to generate frame

synchronization pulses in Frame Master mode if

FRMDLY = 1.

8. SPI Module in Slave Select Mode

The SPI module Slave Select functionality will not

work correctly.

9. SPI Module

The SMP bit does not have any effect when the

SPI module is configured for a 1:1 prescale factor

in Master mode.

PIC24HJXXXGPX06/X08/X10 Rev. A2/A3/A4 Silicon Errata

Summary of content (20 pages)

PAGE 1
PIC24HJXXXGPX06/X08/X10 PIC24HJXXXGPX06/X08/X10 Rev. A2/A3/A4 Silicon Errata The PIC24H (Rev. A2/A3/A4) devices you received were found to conform to the specifications and functionality described in the following documents: • DS70175 – “PIC24H Family Data Sheet” • DS70157 – “dsPIC30F/33F Programmer’s Reference Manual” • DS70046 – “dsPIC30F Family Reference Manual” The exceptions to the specifications in the documents listed above are described in this section.
PAGE 2
PIC24HJXXXGPX06/X08/X10 10. ECAN™ Module ECAN transmissions may be incorrect if multiple transmit buffers are simultaneously queued for transmission. 11. ECAN Module Under specific conditions, the first five bits of a transmitted identifier may not match the value in the transmit buffer ID register. 12. ECAN Module Loopback Mode The ECAN module (ECAN1 or ECAN2) does not function correctly in Loopback mode. 13.
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PIC24HJXXXGPX06/X08/X10 38. DMA NULL Data Peripheral Write mode for the DMA channel does not function. 39. DMA DMA request Fault condition does not generate a DMA error trap. 40. DMA DMA channel writes an additional NULL value to the peripheral register. 41. REPEAT Instruction Any instruction executed inside a REPEAT loop that produces a Read-After-Write stall condition, results in the instruction being executed fewer times than was intended. 42.
PAGE 4
PIC24HJXXXGPX06/X08/X10 1. Module: Doze Mode Enabling Doze mode slows down the CPU but allows peripherals to run at full speed. When the CPU clock is slowed down by enabling Doze mode (CLKDIV<11> = 1), any writes to a peripheral SFR can cause other updates to that register to cease to function for the duration of the current CPU clock cycle. This is only an issue if the CPU attempts to write to the same register as a peripheral while in Doze mode.
PAGE 5
PIC24HJXXXGPX06/X08/X10 2. Module: 12-bit ADC When the ADC module is configured for 12-bit operation, the specifications in the data sheets are not met. Work around Implement the ADC module as an 11-bit ADC with a maximum conversion rate of 300 ksps. 1. The specifications in Table 1 reflect 11-bit ADC operation. RIN source impedance is recommended as 200 ohms and sample time is recommended as 3 TAD to ensure compatibility on future enhanced ADC modules. Missing codes are possible every 27 codes. 2.
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PIC24HJXXXGPX06/X08/X10 3. Module: 10-bit ADC When the ADC module is configured for 10-bit operation, the specifications in the data sheet are not met for operation above 500 ksps. For 500 ksps, the module meets specifications except for Gain and Offset parameters AD23bb and AD24bb. For 600 ksps operation, the module specifications are shown in Table 2. Work around None. Future versions of the silicon will support the ADC performance stated in the data sheet. TABLE 2: 600 KSPS OPERATION Param No.
PAGE 7
PIC24HJXXXGPX06/X08/X10 4. Module: DMA Module: Interaction with EXCH Instruction The EXCH instruction does not execute correctly when either of the two operands is numerically equal to the address of any of the DMAC SFRs for this revision of silicon.
PAGE 8
PIC24HJXXXGPX06/X08/X10 8. Module: SPI in Slave Select Mode The SPI module Slave Select functionality (enabled by setting SSEN = 1) will not function correctly. Whether the SSx pin (x = 1 or 2) is high or low, the SPI data transfer will be completed and an interrupt will be generated. Work around If DMA is not being used, poll the SSx pin state using the Change Notification (CN) pin associated to the SSx pin as follows: 1. Disable the SPIx module by clearing the SPIEN bit in the SPIxSTAT register. 2.
PAGE 9
PIC24HJXXXGPX06/X08/X10 13. Module: I2C The Bus Collision Status bit (BCL) does not get set when a bus collision occurs during a Restart or Stop event. However, the BCL bit gets set when a bus collision occurs during a Start event. Work around None. 14. Module: INT0, ADC and Sleep/Idle Mode ADC event triggers from the INT0 pin will not wake-up the device from Sleep or Idle mode if the SMPI bits are non-zero.
PAGE 10
PIC24HJXXXGPX06/X08/X10 22. Module: UART With the auto-baud feature selected, the sync break character (0x55) may be loaded into the FIFO as data. Work around To prevent the sync break character from being loaded into the FIFO, load the UxBRG register with either 0x0000 or 0xFFFF prior to enabling the auto-baud feature (ABAUD = 1). 23. Module: I2C Writing to I2CxTRN during a Start bit transmission generates a write collision, indicated by the IWCOL (I2CxSTAT<7>) bit being set.
PAGE 11
PIC24HJXXXGPX06/X08/X10 29. Module: FRC Oscillator The device does not meet the internal FRC accuracy specifications in the data sheet (Table 23-18 of the “PIC24H Family Data Sheet” (DS70175)). The actual accuracy specifications are shown in Table 3. Work around None. TABLE 3: INTERNAL FRC ACCURACY AC Characteristics Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C < TA < +85°C for industrial Parameter No.
PAGE 12
PIC24HJXXXGPX06/X08/X10 30. Module: SPI SPI1 functionality for pin 34 (U1RX/SDI1/RF2) is enabled by the SPI2 module. As a result, two side effects occur: 1. RF2 functionality is disabled if the SPI2 module is enabled. 2. This pin will not function as SDI1 if the SPI1 module is enabled. This issue affects 64-pin devices only: • • • • • • PIC24HJ64GP206 PIC24HJ128GP206 PIC24HJ256GP206 PIC24HJ128GP306 PIC24HJ64GP506 PIC24HJ128GP506 Work around Two conditions apply: 1.
PAGE 13
PIC24HJXXXGPX06/X08/X10 33. Module: DMA When a DMA channel is enabled in Single-Shot mode while the device is in Idle mode, and the corresponding peripheral is active and configured to operate during Idle mode, the DMA channel may not become disabled immediately upon transferring the required amount of data. As a result, the number of bytes or words of data transferred may exceed the DMA transfer count specified in the DMAxCNT register.
PAGE 14
PIC24HJXXXGPX06/X08/X10 40. Module: DMA When the DMA channel is configured for One Shot mode with NULL write enabled, the channel will write an extra NULL to the peripheral register after completing the last transfer. In the case of the SPI module and the SPIxBUF register, this would cause the SPI module to perform an extra receive operation. Work around None.
PAGE 15
PIC24HJXXXGPX06/X08/X10 42. Module: FRC Oscillator For certain values of the TUN<5:0> bits (OSCTUN<5:0>), the resultant frequencies do not match the expected values. As shown in Table 4, the actual frequencies obtained for different values of the TUN<5:0> bits are listed in terms of percentage change relative to the center frequency of 7.3728 MHz. The frequency errors listed in the table are approximate and may vary slightly from device to device.
PAGE 16
PIC24HJXXXGPX06/X08/X10 43. Module: UART 48. Module: I2C When the UART is configured for IR interface operations (UxMODE<9:8> = 11), the 16x baud clock signal on the BCLK pin is present only when the module is transmitting. The pin is idle at all other times. With the I2C module enabled, the PORT bits and external interrupt input functions (if any) associated with the SCL and SDA pins do not reflect the actual digital logic levels on the pins.
PAGE 17
PIC24HJXXXGPX06/X08/X10 52. Module: PSV Operations An address error trap occurs in certain addressing modes when accessing the first four bytes of an PSV page. This only occurs when using the following addressing modes: • MOV.D • Register Indirect Addressing (word or byte mode) with pre/post-decrement Work around Do not perform PSV accesses to any of the first four bytes using the above addressing modes. For applications using the C language, MPLAB C30 version 3.
PAGE 18
PIC24HJXXXGPX06/X08/X10 APPENDIX A: REVISION HISTORY Revision A (6/2006) Initial release of the document. Revision B (12/2006) Added issues 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, and 17. Revision C (3/2007) Changed document title, updated issue 8, and added issues 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 and 31. Revision D (6/2007) Added the following silicon issues: 32 (SPI), 33 (UART), 34 (Device ID Register), 35 (DMA), 36 (Doze Mode and Traps) and 37 (DCI).
PAGE 19
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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