Information
© 2008 Microchip Technology Inc. DS80326D-page 1
PIC24HJ12GP201/202
The PIC24HJ12GP201/202 (Rev. A2/A3/A4) devices
you received were found to conform to the specifica-
tions and functionality described in the following docu-
ments:
•“PIC24HJ12GP201/202 Data Sheet” (DS70282)
•“dsPIC30F/33F Programmer’s
Reference Manual” (DS70157)
The exceptions to the specifications in the documents
listed above are described in this section. The specific
devices for which these exceptions are described are
listed below:
• PIC24HJ12GP201
• PIC24HJ12GP202
PIC24HJ12GP201/202 Rev. A2/A3/A4 silicon is
identified by performing a “Reset and Connect”
operation to the device using MPLAB
®
ICD 2 or
MPLAB REAL ICE™ in-circuit emulator, with MPLAB
IDE v7.60 or later. The output window will show a
successful connection to the device specified in
Configure>Select Device. The resulting DEVREV
register values for Rev. A2/A3/A4 silicon are 0x3001,
0x3002, and 0x3003, respectively.
The errata described in this document will be
addressed in future revisions of silicon.
Silicon Errata Summary
The following list summarizes the errata described in
further detail in the remainder of this document:
1. JTAG Programming
JTAG programming does not work.
2. UART
UART receptions may be corrupted if the Baud
Rate Generator (BRG) is set up for 4x mode.
3. UART
The auto-baud feature may not calculate the
correct baud rate when the BRG is set up for 4x
mode.
4. UART
With the auto-baud feature selected, the Sync
Break character (0x55) may be loaded into the
FIFO as data.
5. UART
The auto-baud feature measures baud rate
inaccurately for certain baud rate and clock speed
combinations.
6. Traps and Idle Mode
If a clock failure occurs when the device is in Idle
mode, the oscillator failure trap does not vector to
the Trap Service Routine (TSR).
7. UART
When an auto-baud is detected, the receive
interrupt may occur twice.
8. UART
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
9. UART Module
The 16x baud clock signal on the BCLK pin is
present only when the module is transmitting.
10. SPI Module
The SPIxCON1 DISSCK bit does not influence
port functionality.
11. I
2
C™ Module
The BCL bit in I2CSTAT can only be cleared with a
16-bit operation, and can be corrupted with 1-bit or
8-bit operations on I2CSTAT.
PIC24HJ12GP201/202 Rev. A2/A3/A4 Silicon Errata