Information

© 2010-2011 Microchip Technology Inc. DS80466F-page 7
PIC24HJ12GP201/202
20. Module: I
2
C
In 10-bit Addressing mode, some address
matches do not set the RBF flag or load the
receive register, I2CxRCV, if the lower address
byte matches the reserved addresses. In
particular, these include all addresses with the
form XX0000XXXX and XX1111XXXX, with the
following exceptions:
001111000X
011111001X
101111010X
111111011X
Work around
Ensure that the lower address byte in 10-bit
Addressing mode does not match any 7-bit
reserved addresses.
Affected Silicon Revisions
21. Module: I
2
C
When the I
2
C module is operating in either Master
or Slave mode, after the ACKSTAT bit is set when
receiving a NACK, it may be cleared by the
reception of a Start or Stop bit.
Work around
Store the value of the ACKSTAT bit immediately
after receiving a NACK.
Affected Silicon Revisions
22. Module: CPU
The EXCH instruction does not execute correctly.
Work around
If writing source code in assembly, the
recommended work around is to replace:
EXCH Wsource, Wdestination
with:
PUSH Wdestination
MOV Wsource, Wdestination
POP Wsource
If using the MPLAB C30 C compiler, specify the
compiler option: -merrata=exch (Project > Build
Options > Projects > MPLAB C30 > Use Alternate
Settings).
Affected Silicon Revisions
23. Module: UART
The UART module will not generate consecutive
break characters. Trying to perform a back-to-back
Break character transmission will cause the UART
module to transmit the dummy character used to
generate the first Break character instead of
transmitting the second Break character. Break
characters are generated correctly if they are
followed by non-Break character transmission.
Work around
None.
Affected Silicon Revisions
24. Module: SPI
Regardless of the Slave setting for the Frame
delay bit (FRMDLY = 0 or FRMDLY = 1), the Slave
always acts as if the sync pulse precedes the first
SPI data bit (FRMDLY = 0). The SPI will not
function as described if Slave FRMDLY = 1.
Work around
None.
Affected Silicon Revisions
A2 A3 A4 A5
XXXX
A2 A3 A4 A5
XXX
X
A2 A3 A4 A5
XXXX
A2 A3 A4
A5
XXXX
A2 A3 A4 A5
XXXX