Information

© 2010-2011 Microchip Technology Inc. DS80466F-page 3
PIC24HJ12GP201/202
I
2
C — 19. With the I
2
C module enabled, the port bits and external
interrupt input functions (if any) associated with SCL and
SDA pins do not reflect the actual digital logic levels on the
pins.
XXXX
I
2
C 10-bit
Addressing
20. The 10-bit slave does not set the RBF flag or load the
I2CxRCV register on address match if the Least Significant
bits (LSbs) of the address are the same as the 7-bit
reserved addresses.
XXXX
I
2
C — 21. After the ACKSTAT bit is set when receiving a NACK, it
may be cleared by the reception of a Start or Stop bit.
XXXX
CPU EXCH
Instruction
22. The EXCH instruction does not execute correctly. X X X X
UART Break
Character
Generation
23. The UART module will not generate back-to-back Break
characters.
XXXX
SPI Slave
FRMDLY
24. The SPI communication in Framed mode does not function
correctly if the Slave SPI frame delay bit (FRMDLY) is set
to ‘1’.
XXXX
ADC Current
Consumption
in Sleep
Mode
25. If the ADC module is in an enabled state when the device
enters Sleep mode, the power-down current (IPD) of the
device may exceed the device data sheet specifications.
XXXX
CPU div.sd 26. When using the div.sd instruction, the overflow bit is not
getting set when an overflow occurs.
XXXX
UART TX Interrupt 27. A transmit (TX) Interrupt may occur before the data
transmission is complete.
XXXX
JTAG Flash
Programming
28. JTAG Flash programming is not supported. X X X X
TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature
Item
Number
Issue Summary
Affected
Revisions
(1)
A2 A3 A4 A5
Note 1: Only those issues indicated in the last column apply to the current silicon revision.