Datasheet

 2010 Microchip Technology Inc. DS39940D-page 347
PIC24FJ64GB004 FAMILY
RTCC
Alarm Configuration .................................................. 250
Alarm Mask Settings (figure)..................................... 251
Calibration................................................................. 250
Register Mapping...................................................... 242
Selecting Clock Source............................................. 242
Source Clock............................................................. 241
Write Lock ................................................................. 242
S
Selective Peripheral Power Control .................................. 125
Serial Peripheral Interface. See SPI.
SFR Space.......................................................................... 34
Software Simulator (MPLAB SIM)..................................... 295
Software Stack.................................................................... 50
Special Features ................................................................. 10
SPI
T
Timer1............................................................................... 149
Timer2/3 and Timer4/5...................................................... 151
Timing Diagrams
CLKO and I/O Timing................................................ 322
External Clock........................................................... 320
Trap Service Routine (TSR).............................................. 106
Triple Comparator ............................................................. 269
U
UART ................................................................................ 189
Baud Rate Generator (BRG)..................................... 190
IrDA Support ............................................................. 191
Operation of UxCTS
and UxRTS Pins ...................... 191
Receiving
8-Bit or 9-Bit Data Mode ................................... 191
Transmitting
8-Bit Data Mode................................................ 191
9-Bit Data Mode................................................ 191
Break and Sync Sequence ............................... 191
Universal Asynchronous Receiver Transmitter. See UART.
Universal Serial Bus
Buffer Descriptors
Assignment in Different Buffering Modes ......... 203
Interrupts
and USB Transactions...................................... 207
Universal Serial Bus. See USB OTG.
USB On-The-Go (OTG) ...................................................... 10
USB OTG
Buffer Descriptors and BDT...................................... 202
Device Mode Operation............................................ 207
DMA Interface........................................................... 203
Hardware Configuration
Device Mode..................................................... 199
External Interface ............................................. 201
Host and OTG Modes....................................... 200
Transceiver Power Requirements .................... 201
V
BUS Voltage Generation ................................. 201
Host Mode Operation ............................................... 208
Interrupts .................................................................. 206
OTG Operation ......................................................... 210
Registers .......................................................... 212–230
V
BUS Voltage Generation ......................................... 201
V
VDDCORE/VCAP Pin ........................................................... 287
W
Watchdog Timer (WDT).................................................... 288
Control Register........................................................ 289
Windowed Operation ................................................ 289
WWW Address ................................................................. 348
WWW, On-Line Support ....................................................... 8