Datasheet

PIC24FJ64GB004 FAMILY
DS39940D-page 344  2010 Microchip Technology Inc.
CPU
Arithmetic Logic Unit (ALU)......................................... 29
Clocking Scheme ......................................................108
Control Registers ........................................................ 28
Core Registers ............................................................27
Programmer’s Model................................................... 25
CRC
Registers................................................................... 255
Typical Operation......................................................255
User Interface ........................................................... 254
Data .................................................................. 254
Polynomial ........................................................ 254
CTMU
Measuring Capacitance ............................................ 275
Measuring Time ........................................................ 276
Pulse Delay and Generation ..................................... 276
Customer Change Notification Service ............................. 348
Customer Notification Service........................................... 348
Customer Support ............................................................. 348
D
Data Memory
Address Space............................................................ 33
Memory Map ...............................................................33
Near Data Space ........................................................ 34
SFR Space.................................................................. 34
Software Stack............................................................ 50
Space Organization and Alignment ............................ 34
DC Characteristics
Comparator Specifications........................................ 318
Comparator Voltage Reference ................................ 318
I/O Pin Input Specifications....................................... 316
I/O Pin Output Specifications .................................... 317
Idle Current ............................................................... 311
Internal Voltage Regulator ........................................ 318
Operating Current .....................................................309
Power-Down Base Current ....................................... 313
Power-Down Peripheral Module Current (I
PD).......... 314
Program Memory ......................................................317
Temperature and Voltage Specifications .................. 308
Deep Sleep BOR (DSBOR) ................................................ 67
Deep Sleep Watchdog Timer (DSWDT) ........................... 289
Development Support ....................................................... 293
DISVREG Pin....................................................................287
Doze Mode........................................................................ 125
E
Electrical Characteristics
Absolute Maximum Ratings ...................................... 305
Thermal Conditions................................................... 307
V/F Graphs................................................................ 306
Equations
A/D Conversion Clock Period ................................... 267
Baud Rate Reload Calculation.................................. 183
Calculating the PWM Period ..................................... 165
Calculation for Maximum PWM Resolution............... 165
Estimating USB Transceiver Current
Consumption..................................................... 201
Relationship Between Device and SPI
Clock Speed...................................................... 180
UART Baud Rate with BRGH = 0 ............................. 190
UART Baud Rate with BRGH = 1 ............................. 190
Errata ....................................................................................8
Examples
Baud Rate Error Calculation (BRGH = 0) ................. 190
F
Flash Configuration Words ................................. 32, 279–285
Flash Program Memory ...................................................... 55
and Table Instructions ................................................ 55
Enhanced ICSP Operation ......................................... 56
JTAG Operation.......................................................... 56
Programming Algorithm .............................................. 58
RTSP Operation ......................................................... 56
Single-Word Programming ......................................... 61
I
I/O Ports
Analog Input Voltage Considerations ....................... 128
Analog Port Pins Configuration................................. 128
Input Change Notification ......................................... 129
Open-Drain Configuration......................................... 128
Parallel (PIO) ............................................................ 127
Peripheral Pin Select ................................................ 129
Pull-ups and Pull-Downs........................................... 129
I
2
C
Clock Rates .............................................................. 183
Communicating as Master in a Single
Master Environment ......................................... 181
Reserved Addresses ................................................ 183
Setting Baud Rate When Operating as
Bus Master ....................................................... 183
Slave Address Masking ............................................ 183
Input Capture
32-Bit Mode .............................................................. 158
Operations ................................................................ 158
Synchronous and Trigger Modes.............................. 157
Input Capture with Dedicated Timers ............................... 157
Instruction Set
Overview................................................................... 299
Summary .................................................................. 297
Symbols Used in Opcode Descriptions .................... 298
Instruction-Based Power-Saving Modes........................... 117
Deep Sleep............................................................... 118
Idle............................................................................ 118
Sleep ........................................................................ 117
Inter-Integrated Circuit. See I
2
C. ...................................... 181
Internet Address ............................................................... 348
Interrupt Service Routine (ISR)......................................... 106
Interrupt Vector Table (IVT) ................................................ 69
Interrupts
and Reset Sequence .................................................. 69
Control and Status Registers...................................... 72
Implemented Vectors.................................................. 71
Setup and Service Procedures................................. 106
Trap Vectors ............................................................... 70
Vector Table ............................................................... 70
J
JTAG Interface.................................................................. 291
M
Microchip Internet Web Site.............................................. 348
MPLAB ASM30 Assembler, Linker, Librarian ................... 294
MPLAB Integrated Development Environment Software.. 293
MPLAB PM3 Device Programmer .................................... 296
MPLAB REAL ICE In-Circuit Emulator System ................ 295
MPLINK Object Linker/MPLIB Object Librarian ................ 294