Datasheet

PIC24FJ64GB004 FAMILY
DS39940D-page 314  2010 Microchip Technology Inc.
TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN PERIPHERAL
MODULE CURRENT (I
PD)
DC CHARACTERISTICS
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  T
A  +125°C for Extended
Parameter
No.
Typical
(1)
Max Units Conditions
 Power-Down Current (I
PD): PMD Bits are Set, PMSLP Bit is ‘0’
(2)
DC61 0.2 0.7 A-40°C
2.0V
(3)
31 kHz LPRC Oscillator with
RTCC, WDT, DSWDT or
Timer 1: ILPRC
(5)
DC61a 0.2 0.7 A+25°C
DC61i 0.2 0.7 A+60°C
DC61b 0.23 0.7 A+85°C
DC61m 0.3 1.0 A +125C
DC61c 0.25 0.9 A-40°C
2.5V
(3)
DC61d 0.25 0.9 A+25°C
DC61j 0.25 0.9 A+60°C
DC61e 0.28 0.9 A+85°C
DC61p 0.5 1.2 A +125C
DC61f 0.6 1.5 A-40°C
3.3V
(4)
DC61g 0.6 1.5 A+25°C
DC61k 0.6 1.5 A+60°C
DC61h 0.8 1.5 A+85°C
DC61n 1.0 1.7 A +125C
DC62 0.5 1.0 A-40°C
2.0V
(3)
Low drive strength, 32 kHz Crystal
with RTCC, DSWDT or
Timer1: ISOSC;
SOSCSEL = 01
(5)
DC62a 0.5 1.0 A+25°C
DC62i 0.5 1.0 A+60°C
DC62b 0.5 1.3 A+85°C
DC62m 0.6 1.6 A +125C
DC62c 0.7 1.5 A-40°C
2.5V
(3)
DC62d 0.7 1.5 A+25°C
DC62j 0.7 1.5 A+60°C
DC62e 0.7 1.8 A+85°C
DC62n 0.8 2.1 A +125C
DC62f 1.5 2.0 A-40°C
3.3V
(4)
DC62g 1.5 2.0 A+25°C
DC62k 1.5 2.0 A+60°C
DC62h 1.5 2.5 A+85°C
DC62p 1.9 3.0 A +125C
Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: Peripheral IPD deltas are measured with the device in Sleep mode (all peripherals and clocks shut down).
All I/Os are configured as inputs and pulled high. Only the peripheral or clock being measured is enabled.
PMSLP bit is clear and the Peripheral Module Disable bits (PMD) for all unused peripherals are set.
3: On-chip voltage regulator disabled (DISVREG tied to V
DD).
4: On-chip voltage regulator enabled (DISVREG tied to V
SS). Low-Voltage Detect (LVD) and Brown-out
Detect (BOD) are enabled.
5: The  current is the additional current consumed when the module is enabled. This current should be
added to the base I
PD current.