Datasheet

PIC24FJ64GB004 FAMILY
DS39940D-page 114  2010 Microchip Technology Inc.
8.5 Oscillator Modes and USB
Operation
Because of the timing requirements imposed by USB,
an internal clock of 48 MHz is required at all times while
the USB module is enabled. Since this is well beyond the
maximum CPU clock speed, a method is provided to
internally generate both the USB and system clocks
from a single oscillator source. PIC24FJ64GB004 family
devices use the same clock structure as other PIC24FJ
devices, but include a two-branch PLL system to
generate the two clock signals.
The USB PLL block is shown in Figure 8-2. In this
system, the input from the primary oscillator is divided
down by a PLL prescaler to generate a 4 MHz output.
This is used to drive an on-chip 96 MHz PLL frequency
multiplier to drive the two clock branches. One branch
uses a fixed, divide-by-2 frequency divider to generate
the 48 MHz USB clock. The other branch uses a fixed,
divide-by-3 frequency divider and configurable PLL
prescaler/divider to generate a range of system clock
frequencies. The CPDIV bits select the system clock
speed; available clock options are listed in Table 8-2.
The USB PLL prescaler does not automatically sense
the incoming oscillator frequency. The user must man-
ually configure the PLL divider to generate the required
4 MHz output using the PLLDIV<2:0> Configuration
bits. This limits the choices for primary oscillator
frequency to a total of 8 possibilities, shown in
Table 8-3.
TABLE 8-2: SYSTEM CLOCK OPTIONS
DURING USB OPERATION
TABLE 8-3: VALID PRIMARY OSCILLATOR
CONFIGURATIONS FOR USB
OPERATIONS
FIGURE 8-2: USB PLL BLOCK
8.5.1 CONSIDERATIONS FOR USB
OPERATION
When using the USB On-The-Go module in
PIC24FJ64GB004 family devices, users must always
observe these rules in configuring the system clock:
• For USB operation, the selected clock source
(EC, HS or XT) must meet the USB clock
tolerance requirements.
• The Primary Oscillator/PLL modes are the only
oscillator configurations that permit USB opera-
tion. There is no provision to provide a separate
external clock source to the USB module.
• All oscillator modes are available; however, USB
operation is not possible when these modes are
selected. They may still be useful in cases where
other power levels of operation are desirable and
the USB module is not needed (e.g., the application
is Sleeping and waiting for bus attachment).
MCU Clock Division
(CPDIV<1:0>)
Microcontroller
Clock Frequency
None (00)32MHz
2 (01)16MHz
4 (10)8MHz
8 (11)4MHz
Input Oscillator
Frequency
Clock Mode
PLL Division
(PLLDIV<2:0>)
48 MHz ECPLL 12 (111)
32 MHz ECPLL 8 (110)
24 MHz HSPLL, ECPLL 6 (101)
20 MHz HSPLL, ECPLL 5 (100)
16 MHz HSPLL, ECPLL 4 (011)
12 MHz HSPLL, ECPLL 3 (010)
8 MHz XTPLL, ECPLL 2 (001)
4 MHz XTPLL, ECPLL 1 (000)
PLL
96 MHz
PLL
 3
 2
Prescaler
4 MHz
PLL
Prescaler
48 MHz Clock
for USB Module
PLL Output
for System Clock
CPDIV<1:0>
PLLDIV<2:0>
Input from
POSC
Input from
FRC
FNOSC<2:0>
(4 MHz or
8 MHz)
00
01
10
11
32 MHz
111
110
101
100
011
010
001
000
 12
 8
 8
 6
 5
 4
 3
 2
 1
 4
 2
 1