Datasheet

PIC24FJ128GA310 FAMILY
DS39996F-page 80  2010-2011 Microchip Technology Inc.
REGISTER 5-2: DMACHn: DMA CHANNEL n CONTROL REGISTER
U-0 U-0 U-0 r-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — r —NULLWRELOAD
(1)
CHREQ
(3)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 SIZE CHEN
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 12 Reserved: Maintain as ‘0’
bit 11 Unimplemented: Read as ‘0’
bit 10 NULLW: Null Write Mode bit
1 = A dummy write is initiated to DMASRC for every write to DMADST
0 = No dummy write is initiated
bit 9 RELOAD: Address and Count Reload bit
(1)
1 = DMASRC, DMADST, and DMACNT registers are reloaded to their previous values upon the start
of the next operation
0 = DMASRC, DMADST and DMACNT are not reloaded on the start of the next operation
(2)
bit 8 CHREQ: DMA Channel Software Request bit
(3)
1 = A DMA request is initiated by software; automatically cleared upon completion of a DMA transfer
0 = No DMA request is pending
bit 7-6 SAMODE<1:0>: Source Address Mode Selection bits
11 = DMASRC is used in Peripheral Indirect Addressing and remains unchanged
10 = DMASRC is decremented based on SIZE bit after a transfer completion
01 = DMASRC is incremented based on SIZE bit after a transfer completion
00 = DMASRC remains unchanged after a transfer completion
bit 5-4 DAMODE<1:0>: Destination Address Mode Selection bits
11 = DMADST is used in Peripheral Indirect Addressing and remains unchanged
10 = DMADST is decremented based on SIZE bit after a transfer completion
01 = DMADST is incremented based on SIZE bit after a transfer completion
00 = DMADST remains unchanged after a transfer completion
bit 3-2 TRMODE<1:0>: Transfer Mode Selection bits
11 = Repeated Continuous
10 = Continuous
01 = Repeated One-Shot
00 = One-Shot
bit 1 SIZE: Data Size Selection bit
1 = Byte (8-bit)
0 = Word (16-bit)
bit 0 CHEN: DMA Channel Enable bit
1 = The corresponding channel is enabled
0 = The corresponding channel is disabled
Note 1: Only the original DMACNT is required to be stored to recover the original DMASRC and DMADST.
2: DMASRC, DMADST and DMACNT are always reloaded in Repeated mode transfers (DMACHn<2> = 1),
regardless of the state of the RELOAD bit.
3: The number of transfers executed while CHREQ is set depends on the configuration of TRMODE<1:0>.