Datasheet

2010-2011 Microchip Technology Inc. DS39996F-page 61
PIC24FJ128GA310 FAMILY
TABLE 4-26: REAL-TIME CLOCK AND CALENDAR (RTCC) REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
ALRMVAL 0620 Alarm Value Register Window Based on ALRMPTR<1:0> xxxx
ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000
RTCVAL 0624 RTCC Value Register Window Based on RTCPTR<1:0> xxxx
RCFGCAL 0626 RTCEN
RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 Note 1
RTCPWC 0628 PWCEN PWCPOL PWCPRE PWSPRE RTCLK1 RTCLK0 RTCOUT1 RTCOUT0
Note 1
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The status of the RCFGCAL and RTCPWR registers on POR is ‘0000’, and on other Resets, it is unchanged.
TABLE 4-27: DATA SIGNAL MODULATOR (DSM) REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
MDCON 062A MDEN
—MDSIDL MDOE MDSLR MDOPOL —MDBIT0020
MDSRC 062C
SODIS MS3 MS2 MS1 MS0 000x
MDCAR 062E CHODIS CHPOL CHSYNC
CH3 CH2 CH1 CH0 CLODIS CLPOL CLSYNC CL3 CL2 CL1 CL0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-28: COMPARATORS REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
CMSTAT 0630 CMIDL
C3EVT C2EVT C1EVT C3OUT C2OUT C1OUT 0000
CVRCON 0632
CVREFP CVREFM1 CVREFM0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000
CM1CON 0634 CON COE CPOL
CEVT COUT EVPOL1 EVPOL0 CREF CCH1 CCH0 0000
CM2CON 0636 CON COE CPOL
CEVT COUT EVPOL1 EVPOL0 CREF CCH1 CCH0 0000
CM3CON 0638 CON COE CPOL
CEVT COUT EVPOL1 EVPOL0 CREF CCH1 CCH0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.