Datasheet

PIC24FJ128GA310 FAMILY
DS39996F-page 340  2010-2011 Microchip Technology Inc.
REGISTER 29-4: CW4: FLASH CONFIGURATION WORD 4
U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1
— — — — — — — —
bit 23 bit 16
r-1 r-1 r-1 r-1 r-1 r-1 r-1 R/PO-1
r r r r r r r
DSSWEN
bit 15 bit 8
R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1
DSWDTEN DSBOREN DSWDTOSC DSWDPS4 DSWDPS3 DSWDPS2 DSWDPS1 DSWDPS0
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-16 Unimplemented: Read as ‘1’
bit 15-9 Reserved: Read as ‘1’
bit 8 DSSWEN: Deep Sleep Software Control Select bit
1 = Deep Sleep operation is enabled and controlled by the DSEN bit
0 = Deep Sleep operation is disabled
bit 7 DSWDTEN: Deep Sleep Watchdog Timer Enable bit
1 = Deep Sleep WDT is enabled
0 = Deep Sleep WDT is disabled
bit 6 DSBOREN: Deep Sleep Brown-out Reset Enable bit
1 = BOR is enabled in Deep Sleep mode
0 = BOR is disabled in Deep Sleep mode (remains active in other Sleep modes)
bit 5 DSWDTOSC: Deep Sleep Watchdog Timer Clock Select bit
1 = Clock source is LPRC
0 = Clock source is SOSC