Datasheet

PIC24FJ128GA310 FAMILY
DS39996F-page 336  2010-2011 Microchip Technology Inc.
REGISTER 29-2: CW2: FLASH CONFIGURATION WORD 2
U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1
— — — — — — — —
bit 23 bit 16
R/PO-1 r-1 r-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1
IESO r rALTVRF1ALTVRF0 FNOSC2 FNOSC1 FNOSC0
bit 15 bit 8
R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 r-1 R/PO-1 R/PO-1
FCKSM1 FCKSM0 OSCIOFCN IOL1WAY r r POSCMD1 POSCMD0
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-16 Unimplemented: Read as ‘1’
bit 15 IESO: Internal External Switchover bit
1 = IESO mode (Two-Speed Start-up) is enabled
0 = IESO mode (Two-Speed Start-up) is disabled
bit 14-13 Reserved: Always maintain as ‘1’
bit 12-11 ALTVRF<1:0>
: Alternate VREF/CVREF Pins Selection bits
00 = Voltage reference input, A/D = RB0/RB1, Comparator = RB0/RB1
01 = Voltage reference input, A/D = RB0/RB1, Comparator = RA9, RA10
10 = Voltage reference input, A/D = RA9/RA10, Comparator = RB0, RB1
11 = Voltage reference input, A/D = RA9/RA10, Comparator = RA9, RA10
bit 10-8 FNOSC<2:0>: Initial Oscillator Select bits
111 = Fast RC Oscillator with Postscaler (FRCDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 7-6 FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Configuration bits
1x = Clock switching and Fail-Safe Clock Monitor are disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 5 OSCIOFCN: OSCO Pin Configuration bit
If POSCMD
<1:0> = 11 or 00:
1 = OSCO/CLKO/RC15 functions as CLKO (FOSC/2)
0 = OSCO/CLKO/RC15 functions as port I/O (RC15)
If POSCMD<1:0> =
10 or 01:
OSCIOFCN has no effect on OSCO/CLKO/RC15.
bit 4 IOL1WAY: IOLOCK One-Way Set Enable bit
1 = The IOLOCK bit (OSCCON<6>) can be set once, provided the unlock sequence has been
completed. Once set, the Peripheral Pin Select registers cannot be written to a second time.
0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been
completed