Datasheet

 2010-2011 Microchip Technology Inc. DS39996F-page 311
PIC24FJ128GA310 FAMILY
FIGURE 24-3: 10-BIT A/D CONVERTER ANALOG INPUT MODEL
EQUATION 24-1: A/D CONVERSION CLOCK PERIOD
CPIN
VA
Rs
ANx
I
LEAKAGE
RIC  250
Sampling
Switch
R
SS
CHOLD
VSS
= 4.4 pF
500 nA
Legend: CPIN
VT
ILEAKAGE
RIC
RSS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch Resistance
= Sample/Hold Capacitance (from DAC)
various junctions
Note: The CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if Rs  5 k.
R
SS  3 k
TCY (ADCS + 1)
ADCS =
– 1
T
AD
TCY
Note: Based on TCY = 2/FOSC; Doze mode and PLL are disabled.
T
AD =