Datasheet

 2010-2011 Microchip Technology Inc. DS39996F-page 21
PIC24FJ128GA310 FAMILY
PGEC1 15 19 24 K1 I/O ST In-Circuit Debugger/Emulator/ICSP™ Programming
Clock.
PGED1 16 20 25 K2 I/O ST In-Circuit Debugger/Emulator/ICSP Programming
Data.
PGEC2 17 21 26 L1 I/O ST In-Circuit Debugger/Emulator/ICSP Programming
Clock.
PGED2 18 22 27 J3 I/O ST In-Circuit Debugger/Emulator/ICSP Programming
Data.
PGEC3 11 15 20 H1 I/O ST In-Circuit Debugger/Emulator/ICSP Programming
Clock.
PGED3 12 16 21 H2 I/O ST In-Circuit Debugger/Emulator/ICSP Programming
Data.
PMA0 30 36 44 L8 I/O ST Parallel Master Port Address Bit 0 Input (Buffered
Slave modes) and Output (Master modes).
PMA1 29 35 43 K7 I/O ST Parallel Master Port Address Bit 1 Input (Buffered
Slave modes) and Output (Master modes).
PMA2 8 10 14 F3 O — Parallel Master Port Address (bits<22:2>).
PMA3 6 8 12 F2 O —
PMA4 5 7 11 F4 O —
PMA5 4 6 10 E3 O —
PMA6 16 24 29 K3 O —
PMA7 22 23 28 L2 O —
PMA8 32 40 50 L11 O —
PMA9 31 39 49 L10 O —
PMA10 283442L7O—
PMA11 27 33 41 J7 O —
PMA12 24 30 35 J5 O —
PMA13 232934L5O—
PMA14 45 57 71 C11 O —
PMA15 44 56 70 D11 O —
PMA16 — — 95 C4 O —
PMA17 — — 92 B5 O —
PMA18 — — 40 K6 O —
PMA19 — 14 19 G2 O —
PMA20 — — 59 G10 O —
PMA21 — — 60 G11 O —
PMA22 — 52 66 E11 O —
PMACK1 50 62 77 A10 I ST/TTL Parallel Master Port Acknowledge Input 1.
PMACK2 43 55 69 E10 I ST/TTL Parallel Master Port Acknowledge Input 2.
PMBE0 51 63 78 B9 O — Parallel Master Port Byte Enable 0 Strobe.
PMBE1 — 53 67 E8 O — Parallel Master Port Byte Enable 1 Strobe.
PMCS1 — 13 18 G1 I/O ST/TTL Parallel Master Port Chip Select 1 Strobe.
PMCS2 — — 9 E1 O — Parallel Master Port Chip Select 2 Strobe.
TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
Pin Number/Grid Locator
I/O
Input
Buffer
Description
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
2
C™ = I
2
C/SMBus input buffer