Datasheet

PIC24FJ128GA310 FAMILY
PIC24FJDS39996F-page 16  2010-2011 Microchip Technology Inc.
FIGURE 1-1: PIC24FJ128GA310 FAMILY GENERAL BLOCK DIAGRAM
Instruction
Decode and
Control
16
PCH PCL
16
Program Counter
16-Bit ALU
23
24
Data Bus
Inst Register
16
Divide
Support
Inst Latch
16
EA MUX
Read AGU
Write AGU
16
16
8
Interrupt
Controller
EDS and
Stack
Control
Logic
Repeat
Control
Logic
Data Latch
Data RAM
Address
Latch
Address Latch
Extended Data
Data Latch
16
Address Bus
Literal
23
Control Signals
16
16
16 x 16
W Reg Array
Multiplier
17x17
OSCI/CLKI
OSCO/CLKO
V
DD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
LVD & BOR
(2)
Precision
Reference
Band Gap
FRC/LPRC
Oscillators
Regulators
Voltage
VCAP
PORTA
(1)
PORTC
(1)
(12 I/O)
(8 I/O)
PORTB
(16 I/O)
Note 1:
Not all I/O pins or features are implemented on all device pinout configurations. See Ta b le 1 - 4 for specific implementations by pin count .
2: BOR functionality is provided when the on-board voltage regulator is enabled.
3: These peripheral I/Os are only accessible through remappable pins.
PORTD
(1)
(16 I/O)
Comparators
(3)
Timer2/3
(3)
Timer1
RTCC
IC
A/D
12-Bit
OC/PWM
SPI
I
2
C
Timer4/5
(3)
™
EPMP/PSP
1-7
(3)
ICNs
(1)
UART
REFO
PORTE
(1)
PORTG
(1)
(10 I/O)
(12 I/O)
PORTF
(1)
(10 I/O)
1/2
(3)
1/2
1/2/3/4
(3)
1-7
(3)
CTMU
Digital
LCD
Driver
Space
Program Memory/
Modulator
DMA
Controller
Data
DMA
Data Bus
16
Tab l e D a ta
Access Control
VBAT