Information

PIC24FJ64GA104
DS80000486H-page 6  2009-2013 Microchip Technology Inc.
13. Module: UART
When using UTXISEL<1:0> = 01 (Interrupt when
last character is shifted out of the Transmit Shift
Register) and the final character is being shifted
out through the Transmit Shift Register, the TX
interrupt may occur before the final bit is shifted
out.
Work around
If it is critical that the interrupt processing occurs
only when all transmit operations are complete,
after which, the following work around can be
implemented:
Hold off the interrupt routine processing by adding
a loop at the beginning of the routine that polls the
Transmit Shift Register empty bit, as shown in
Example 1.
Affected Silicon Revisions
14. Module: RTCC
Under certain circumstances, the RTCC may not
be clocked properly when the device is in Deep
Sleep mode. This is observed only when all of the
following are true:
• The RTCC is using the LPRC as its clock
source (RTCOSC = 0);
• The SOSC clock source is disabled
(SOSCSEL<1:0> = 00); and
• RA4 is in a logic low state during entry into
Deep Sleep, either by being driven low as
an output (TRISA4 and LATA4 are both ‘0’),
or being held low as an input.
Work around
This issue does not occur if RA4 is maintained in a
logic high state while the device is in Deep Sleep.
This can be done by driving the pin high as an
output (TRISA4 = 0, LATA4 = 1) or driving the pin
to logic high from an external source while it is
configured as an input.
The issue also does not occur if the SOSC is
configured for one of the Crystal Driver modes
(SOSCSEL = x1).
Either method can be used with the same effect.
Affected Silicon Revisions
EXAMPLE 1: DELAYING THE ISR BY POLLING THE TRMT BIT
A2
X
A2
X
// in UART2 initialization code
...
U2STAbits.UTXISEL0 = 1; // Set to generate TX interrupt when all
U2STAbits.UTXISEL1 = 0; // transmit operations are complete.
...
U2TXInterrupt(void)
{
while(U2STAbits.TRMT==0); // wait for the transmit buffer to be empty
... // process interrupt