Information

PIC24FJ64GA104
DS80000486H-page 4  2009-2013 Microchip Technology Inc.
5. Module: SPI (Master Mode)
When operating in Enhanced Buffer Master mode,
the Transmit Buffer Full flag, SPITBF, may be
cleared before all data in the FIFO buffer has
actually been set. This may result in data being
overwritten before it can be sent.
This has only been observed when the SPIx clock
prescalers are configured for a divider of greater
than 1:4.
This behavior has not been observed when the
module is operating in any other mode.
Work around
Several options are available:
• If possible, use a total clock prescale factor
of 1:4 or less.
• Do not use SPITBF to indicate when new
data can be written to the buffer. Instead,
use the SPIRBF or SPIBEC flags to track
the number of bytes actually transmitted.
• If the SPITBF flag must be used, always
wait at least one-half SPIx clock cycle
before writing to the transmit buffer.
Affected Silicon Revisions
6. Module: Triple (Enhanced) Comparator
When any of the internal band gap options (VBG,
V
BG/2 or VBG/6) are selected by the voltage
reference module as the comparator’s CV
REF-
input, the comparator may not generate an
interrupt when a preprogrammed event is
detected.
The CV
REF+ input works as previously
described.
Work around
If it is necessary to use the internal band gap as
a reference, do the following:
1. Enable the comparator’s output
(CMCON<14> = 1), and map the output to
an available remappable output pin.
2. Connect this pin to any other available pin
that supports either external interrupt or
interrupt-on-change notification.
3. Monitor the second pin for an interrupt
event.
Affected Silicon Revisions
7. Module: Core (Doze Mode)
Operations that immediately follow any manipu-
lations of the DOZE<2:0> or DOZEN bits
(CLKDIV<14:11>) may not execute properly. In
particular, for instructions that operate on an
SFR, data may not be read properly. Also, bits
automatically cleared in hardware may not be
cleared if the operation occurs during this
interval.
Work around
Always insert a NOP instruction before and after
either of the following:
• enabling or disabling Doze mode by setting
or clearing the DOZEN bit
• before or after changing the DOZE<2:0> bits
Affected Silicon Revisions
8. Module: A/D Converter
When using PGEC3 and PGED3 to debug an
application, all voltage references will be disabled.
This includes V
REF+, VREF-, AVDD and AVSS. Any
A/D conversion will always equal 03FFh.
Work around
Use either PGEC1/PGED1 or PGEC2/PGED2
to debug any A/D functionality.
Affected Silicon Revisions
A2
X
A2
X
A2
X
A2
X