Information

 2009-2013 Microchip Technology Inc. DS80000486H-page 3
PIC24FJ64GA104
Silicon Errata Issues
1. Module: Output Compare (Cascaded
Mode)
When using Cascaded (32-bit) mode, Trigger
and Synchronous modes do not work as
expected. The even numbered module does not
become synchronized to the odd numbered
module, resulting in errors in the Most Signifi-
cant 16 bits of the output. In certain modes, the
even numbered module does not generate any
output. This behavior is independent of the
OCTRIG trigger/sync selection for the even
numbered module.
Work around
None.
Affected Silicon Revisions
2. Module: UART
The UART module will not generate consecutive
Break characters. Trying to perform a back-to-
back Break character transmission will cause the
UART module to transmit the dummy character
used to generate the first Break character instead
of transmitting the second Break character. Break
characters are generated correctly if they are
followed by non-Break character transmission.
Work around
None.
Affected Silicon Revisions
3. Module: Oscillator (Secondary Oscillator
Configuration)
Under certain circumstances, applying voltages
to the comparator inputs, C2INC and C2IND
(SOSCO/RA4 and SOSCI/RB4, respectively),
may cause the microcontroller’s current draw to
increase. This happens only when all of the
following conditions are met:
• RA4 and RB4 are configured to function as
digital I/O, rather than as Secondary
Oscillator pins (SOSCSEL<1:0> = 00);
• the pins are configured as digital inputs
(TRIS<4> and TRISB<4> = 1); and
• the voltage applied to the pins approaches
1/2 V
DD.
This occurs regardless of the signal source; a
comparator input voltage or a digital clock input
of sufficient amplitude will have the same result.
Work around
If it is necessary to use RA4 and RB4 as
comparator inputs, C2INC and C2IND, program
the SOSCSEL Configuration bits (CW3<9:8>)
for one of the oscillator modes, rather than
digital I/O (SOSCSEL<1:0> = 11 or 01).
Affected Silicon Revisions
4. Module: SPI (Master Mode)
When operating in Enhanced Buffer Master mode,
the module may transmit two bytes or two words of
data, with a value of 0h, immediately upon the
microcontroller waking up from Sleep mode. At the
same time, the module “receives” two words or two
bytes of data, also with the value of 0h.
The transmission of null data occurs even if the
Transmit Buffer registers are empty prior to the
microcontroller entering Sleep mode. The
received null data requires that the receive buffer
be read twice to clear the “received” data.
This behavior has not been observed when the
module is operating in any other mode.
Work around
When operating in Enhanced Buffer Master mode,
disable the module (SPIEN = 0) before entering
Sleep mode.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A2).
A2
X
A2
X
A2
X
A2
X