Information

PIC24FJ64GA104
DS80000486H-page 2  2009-2013 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature
Item
Number
Issue Summary
Affected
Revisions
(1)
A2
Output
Compare
Cascaded
mode
1. Cascaded mode does not work as expected. X
UART Break
Character
Generation
2. Will not generate back-to-back Break characters. X
Oscillator Secondary
Oscillator
Configuration
3. High-current draw when external signal applied under
certain conditions.
X
SPI Master mode 4. Spurious transmission and reception of null data on wake-up
from Sleep (Master mode).
X
SPI Master mode 5. Inaccurate SPITBF flag with high clock divider. X
Triple
(Enhanced)
Comparator
— 6. No interrupt generation with internal band gap reference. X
Core Doze Mode 7. Instruction execution glitches following DOZE bit changes. X
A/D Converter — 8. Disabled voltage references during Debug mode. X
Interrupts INTx 9. External interrupts missed when writing to INTCON2. X
Oscillator — 10. POSCEN bit does not work with Primary + PLL modes. X
A/D Converter — 11. Module continues to draw current when disabled. X
Output
Compare
Interrupt 12. Interrupt flag may precede the output pin change under
certain circumstances.
X
UART Transmit 13. A TX Interrupt may occur before the data transmission is
complete.
X
RTCC — 14. LPRC does not clock RTCC in Deep Sleep, under certain
circumstances.
X
Note 1: Only those issues indicated in the last column apply to the current silicon revision.