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ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SPDIP 28 16-Bit 32 MHz I/O number 21

 2009-2013 Microchip Technology Inc. DS80000486H-page 1

PIC24FJ64GA104 FAMILY

The PIC24FJ64GA104 family devices that you have

received conform functionally to the current Device Data

Sheet (DS39951C), except for the anomalies described

in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Tabl e 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be addressed

in future revisions of the PIC24FJ64GA104 silicon.

Data Sheet clarifications and corrections start on Page 7,

following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s

programmers, debuggers, and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 2 or

PICkit™ 3:

1. Using the appropriate interface, connect the

device to the MPLAB ICD 2 programmer/

debugger or PICkit™ 3.

2. From the main menu in MPLAB IDE, select

Configure>Select Device

, and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Debugger>Select Tool

4. Perform a “Connect” operation to the device

(Debugger>Connect

). Depending on the devel-

opment tool used, the part number and Device

Revision ID value appear in the Output window.

The DEVREV values for the various PIC24FJ64GA104

silicon revisions are shown in Tabl e 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (A2).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID

(1)

Revision ID for Silicon

Revision

(2)

PIC24FJ32GA102 4202h

0002h

PIC24FJ32GA104 420Ah

PIC24FJ64GA102 4206h

PIC24FJ64GA104 420Eh

Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses in program

memory. They are shown in hexadecimal in the format “DEVID DEVREV”.

2: Refer to the “PIC24FJ64GA1/GB0 Families Flash Programming Specification” (DS39934) for detailed

information on Device and Revision IDs for your specific device.

PIC24FJ64GA104 Family

Silicon Errata and Data Sheet Clarification

Summary of content (14 pages)

PAGE 1
PIC24FJ64GA104 FAMILY PIC24FJ64GA104 Family Silicon Errata and Data Sheet Clarification The PIC24FJ64GA104 family devices that you have received conform functionally to the current Device Data Sheet (DS39951C), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2.
PAGE 2
PIC24FJ64GA104 TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Affected Revisions(1) Issue Summary A2 Output Compare Cascaded mode 1. Cascaded mode does not work as expected. X UART Break Character Generation 2. Will not generate back-to-back Break characters. X Oscillator Secondary Oscillator Configuration 3. High-current draw when external signal applied under certain conditions. X SPI Master mode 4.
PAGE 3
PIC24FJ64GA104 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A2). 1. Module: Output Compare (Cascaded Mode) When using Cascaded (32-bit) mode, Trigger and Synchronous modes do not work as expected.
PAGE 4
PIC24FJ64GA104 5. Module: SPI (Master Mode) 7. Module: Core (Doze Mode) When operating in Enhanced Buffer Master mode, the Transmit Buffer Full flag, SPITBF, may be cleared before all data in the FIFO buffer has actually been set. This may result in data being overwritten before it can be sent. This has only been observed when the SPIx clock prescalers are configured for a divider of greater than 1:4. This behavior has not been observed when the module is operating in any other mode.
PAGE 5
PIC24FJ64GA104 9. Module: Interrupts (INTx) 11. Module: A/D Converter Writing to the INTCON2 register may cause an external interrupt event (inputs on INT0 through INT2) to be missed. This only happens when the interrupt event and the write event occur during the same clock cycle. Once the A/D module is enabled (AD1CON1<15> = 1), it may continue to draw extra current even if the module is later disabled (AD1CON1<15> = 0).
PAGE 6
PIC24FJ64GA104 13. Module: UART 14. Module: RTCC When using UTXISEL<1:0> = 01 (Interrupt when last character is shifted out of the Transmit Shift Register) and the final character is being shifted out through the Transmit Shift Register, the TX interrupt may occur before the final bit is shifted out. Under certain circumstances, the RTCC may not be clocked properly when the device is in Deep Sleep mode.
PAGE 7
PIC24FJ64GA104 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS39951C): Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. Note: Designers may use Figure 2-3 to evaluate ESR equivalence of candidate devices. 1. Module: Guidelines for Getting Started with 16-Bit Microcontrollers Section 2.
PAGE 8
PIC24FJ64GA104 CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller.
PAGE 9
PIC24FJ64GA104 2. Module: Electrical Characteristics Changes, shown in bold, have been made to the DC10 and DC18 rows in Table 28-3. The updated table is shown below: TABLE 28-3 DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: Operating temperature DC CHARACTERISTICS Param No. 2.0V to 3.6V (unless otherwise stated) -40°C < TA < +85°C for Industrial -40°C < TA < +125°C for Extended Min Typ(1) Max Units VDD VBORMIN — 3.6 V VDD VDDCORE — 3.
PAGE 10
PIC24FJ64GA104 3. Module: Electrical Specifications Table 28-8 (I/O Pin Input Specifications) is amended by the addition of the following new specifications: • DI31 (Maximum Load Current for Internal Pull-up) • DI60 (Injection Currents) The new specifications, and accompanying new footnotes, 5 through 9, are shown below (additions in bold; bold in existing text has been removed for clarity).
PAGE 11
PIC24FJ64GA104 4. Module: Electrical Specifications In Table 28-19, parameter F20 has been amended with two temperature ranges. The changes are shown below in bold (bold text in original removed for clarity). TABLE 28-19: INTERNAL RC OSCILLATOR ACCURACY Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
PAGE 12
PIC24FJ64GA104 APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (10/2009) Initial release of this document; issued for revision A2. Includes silicon issues 1 (Output Compare – Cascaded Mode), 2 (Power-Saving Modes – Sleep Mode) and 3 (UART). Rev B Document (12/2009) Deletes silicon issue 2 (Power-Saving Modes – Sleep Mode); subsequent issues re-numbered accordingly.
PAGE 13
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 14
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