Datasheet

 2010 Microchip Technology Inc. DS39951C-page 227
PIC24FJ64GA104 FAMILY
EQUATION 21-1: A/D CONVERSION CLOCK PERIOD
(1)
FIGURE 21-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL
Note 1: Based on TCY = 2 * TOSC, Doze mode and PLL are disabled.
T
AD = TCY • (ADCS + 1)
TAD
TCY
ADCS = – 1
CPIN
VA
Rs
ANx
V
T = 0.6V
VT = 0.6V
I
LEAKAGE
RIC  250
Sampling
Switch
R
SS
CHOLD
= ADC capacitance
V
SS
VDD
= 4.4 pF (Typical)
500 nA
Legend: CPIN
VT
ILEAKAGE
RIC
RSS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch Resistance
= Sample/Hold Capacitance (from DAC)
various junctions
Note: CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if Rs  5 k.
RSS  5 k(Typical)
6-11 pF
(Typical)