Datasheet

PIC24FJ64GA104 FAMILY
DS39951C-page 226  2010 Microchip Technology Inc.
REGISTER 21-6: AD1CSSL: A/D INPUT SCAN SELECT REGISTER
R/W-0 R/W-0 R/W-0 R/W-0
(1)
R/W-0 R/W-0 R/W-0 R/W-0
CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8
(1)
bit 15 bit 8
R/W
-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CSSL15: A/D Input Band Gap Scan Enable bit
1 = Internal band gap (V
BG) channel is enabled for input scan
0 = Analog channel is disabled from input scan
bit 14 CSSL14: A/D Input Half Band Gap Scan Enable bit
1 = Internal half band gap (V
BG/2) channel is enabled for input scan
0 = Analog channel is disabled from input scan
bit 13 CSSL13: A/D Input Voltage Regulator Output Scan Enable bit
1 = Internal voltage regulator output (V
DDCORE) is enabled for input scan
0 = Analog channel is disabled from input scan
bit 12-0 CSSL<12:0>: A/D Input Pin Scan Selection bits
(1)
1 = Corresponding analog channel is selected for input scan
0 = Analog channel is omitted from input scan
Note 1: Analog channels, AN6, AN7, AN8 and AN12, are unavailable on 28-pin devices; leave these corresponding
bits cleared.