PIC24FJ64GA104 Family Data Sheet 28/44-Pin, 16-Bit General Purpose Flash Microcontrollers with nanoWatt XLP Technology 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC24FJ64GA104 FAMILY 28/44-Pin, 16-Bit General Purpose Flash Microcontrollers with nanoWatt XLP Technology Power Management Modes: Special Microcontroller Features (continued): • Selectable Power Management modes with nanoWatt XLP Technology for Extremely Low Power: - Deep Sleep mode allows near total power-down (20 nA typical and 500 nA with RTCC or WDT), along with the ability to wake-up on external triggers, or self-wake on programmable WDT or RTCC alarm - Extreme low-power DSBOR for Deep Sleep, LPBOR
PIC24FJ64GA104 FAMILY Peripheral Features: • Two UART modules: - Supports RS-485, RS-232 and LIN/J2602 - On-chip hardware encoder/decoder for IrDA® - Auto-wake-up on Start bit - Auto-Baud Detect (ABD) - 4-level deep FIFO buffer • Five 16-Bit Timers/Counters with Programmable Prescaler • Five 16-Bit Capture Inputs, each with a Dedicated Time Base • Five 16-Bit Compare/PWM Outputs, each with a Dedicated Time Base • Programmable, 32-Bit Cyclic Redundancy Check (CRC) Generator • Configurable Open-Drain Outputs
PIC24FJ64GA104 FAMILY AN1/C3IND/VREF-/CN3/CTED2/RA1 AN0/C3INC/VREF+/CN2/CTED1/RA0 MCLR 28-Pin QFN(1,3) VDD VSS AN9/C3INA/RP15/CN11/PMCS1/RB15 AN10/C3INB/CVREF/RTCC/RP14/CN12/PMWR/RB14 Pin Diagrams 28 27 26 25 24 23 22 AN5/C1INA/SCL2/RP3/CN7/RB3 VSS OSCI/CLKI/C1IND/CN30/RA2 OSCO/CLKO/CN29/PMA0/RA3 PIC24FJXXGA102 SOSCI/C2IND/RP4/PMBE/CN1/RB4 8 Legend: Note 1: 2: 3: 9 10 11 12 13 14 21 20 19 18 17 16 15 AN11/C1INC/RP13/CN13/PMRD/REFO/RB13 AN12/RP12/CN14/PMD0/RB12 PGEC2/TMS/RP11/CN15/PMD1/RB11 PGED
PIC24FJ64GA104 FAMILY RP8/SCL1/CN22/PMD4/RB8 RP7/INT0/CN23/PMD5/RB7 PGEC3/RP6/ASCL1(2)/CN24/PMD6/RB6 PGED3/RP5/ASDA1(2)/CN27/PMD7/RB5 VDD VSS RP21/CN26/PMA3/RC5 RP20/CN25/PMA4/RC4 RP19/CN28/PMBE/RC3 TDI/PMA9/RA9 SOSCO/SCLKI/T1CK/C2INC/CN0/RA4 Pin Diagrams 44-PIN TQFP, 44 43 42 41 40 39 38 37 36 35 34 44-Pin QFN(1,3) PIC24FJXXGA104 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 SOSCI/C1IND/RP4/CN1/RB4 TDO/PMA8/RA8 OSCO/CLKO/CN29/RA3 OSCI/CLKI/C1IND/CN30/RA
PIC24FJ64GA104 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 19 3.0 CPU ...................................................................................................
PIC24FJ64GA104 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC24FJ64GA104 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24FJ32GA102 • PIC24FJ32GA104 • PIC24FJ64GA102 • PIC24FJ64GA104 The PIC24FJ64GA104 family provides an expanded peripheral feature set and a new option for high-performance applications which may need more than an 8-bit platform, but do not require the power of a digital signal processor. 1.1 1.1.
PIC24FJ64GA104 FAMILY 1.2 Other Special Features • Peripheral Pin Select: The Peripheral Pin Select feature allows most digital peripherals to be mapped over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many digital peripherals to any one of the I/O pins. • Communications: The PIC24FJ64GA104 family incorporates a range of serial communication peripherals to handle a range of application requirements.
PIC24FJ64GA104 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ64GA104 FAMILY Features PIC24FJ32GA102 PIC24FJ64GA102 PIC24FJ32GA104 PIC24FJ64GA104 Operating Frequency Program Memory (bytes) Program Memory (instructions) DC – 32 MHz 32K 64K 11,008 22,016 Data Memory (bytes) 64K 11,008 22,016 8,192 Interrupt Sources (soft vectors/ NMI traps) I/O Ports 32K 45 (41/4) Ports A and B Ports A, B, C Total I/O Pins 21 35 Remappable Pins 16 26 Timers: 5(1) Total Number (16-bit) 32-Bit (from p
PIC24FJ64GA104 FAMILY FIGURE 1-1: PIC24FJ64GA104 FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller PORTA(1) 16 (9 I/O) 16 16 8 Data Latch PSV & Table Data Access Control Block Data RAM PCH PCL Program Counter Repeat Stack Control Control Logic Logic 23 Address Latch PORTB (16 I/O) 16 23 16 Read AGU Write AGU Address Latch PORTC(1) Program Memory (10 I/O) Data Latch 16 EA MUX Literal Data Address Bus 24 Inst Latch 16 16 RP(1) Inst Register RP0:RP25 Instruction Decode & C
PIC24FJ64GA104 FAMILY TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS Pin Number Function 28-Pin SPDIP/ SOIC/SSOP 28-Pin QFN 44-Pin QFN/ TQFP I/O Input Buffer AN0 2 27 19 I ANA AN1 3 28 20 I ANA AN2 4 1 21 I ANA AN3 5 2 22 I ANA AN4 6 3 23 I ANA AN5 7 4 24 I ANA AN6 — — 25 I ANA AN7 — — 26 I ANA AN8 — — 27 I ANA AN9 26 23 15 I ANA AN10 25 22 14 I ANA AN11 24 21 11 I ANA AN12 23 20 10 I ANA ASCL1 15 12 42 I/O I2C
PIC24FJ64GA104 FAMILY TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 28-Pin SPDIP/ SOIC/SSOP 28-Pin QFN 44-Pin QFN/ TQFP I/O Input Buffer CN0 12 9 34 I ST CN1 11 8 33 I ST CN2 2 27 19 I ST CN3 3 28 20 I ST CN4 4 1 21 I ST CN5 5 2 22 I ST CN6 6 3 23 I ST Description Interrupt-on-Change Inputs.
PIC24FJ64GA104 FAMILY TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin SPDIP/ SOIC/SSOP 28-Pin QFN 44-Pin QFN/ TQFP I/O Input Buffer INT0 16 13 43 I ST External Interrupt Input. MCLR 1 26 18 I ST Master Clear (device Reset) Input. This line is brought low to cause a Reset. Function Description OSCI 9 6 30 I ANA Main Oscillator Input Connection. OSCO 10 7 31 O ANA Main Oscillator Output Connection.
PIC24FJ64GA104 FAMILY TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Input Buffer 28-Pin SPDIP/ SOIC/SSOP 28-Pin QFN RA0 2 27 19 I/O ST RA1 3 28 20 I/O ST RA2 9 6 30 I/O ST RA3 10 7 31 I/O ST RA4 12 9 34 I/O ST RA7 — — 13 I/O ST RA8 — — 32 I/O ST Function 44-Pin QFN/ TQFP I/O RA9 — — 35 I/O ST RA10 — — 12 I/O ST RB0 4 1 21 I/O ST RB1 5 2 22 I/O ST RB2 6 3 23 I/O ST RB3 7 4 24 I/O ST RB4 11 8
PIC24FJ64GA104 FAMILY TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin SPDIP/ SOIC/SSOP 28-Pin QFN 44-Pin QFN/ TQFP I/O Input Buffer RP0 4 1 21 I/O ST RP1 5 2 22 I/O ST RP2 6 3 23 I/O ST Function Description Remappable Peripheral (input or output).
PIC24FJ64GA104 FAMILY TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 28-Pin SPDIP/ SOIC/SSOP 28-Pin QFN 44-Pin QFN/ TQFP I/O Input Buffer Description VCAP 20 17 7 P — External Filter Capacitor Connection (regulator enabled). VDD 13, 28 10, 25 28, 40 P — Positive Supply for Peripheral Digital Logic and I/O Pins. VDDCORE 20 17 7 P — Positive Supply for Microcontroller Core Logic (regulator disabled).
PIC24FJ64GA104 FAMILY • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • ENVREG/DISVREG and VCAP/VDDCORE pins (PIC24FJ devices only) (see Section 2.
PIC24FJ64GA104 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC24FJ64GA104 FAMILY Note: Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE) FIGURE 2-3: The on-chip voltage regulator enable/disable pin (ENVREG or DISVREG, depending on the device family) must always be connected directly to either a supply voltage or to ground.
PIC24FJ64GA104 FAMILY 2.6 External Oscillator Pins FIGURE 2-4: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency Secondary Oscillator (refer to Section 8.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
PIC24FJ64GA104 FAMILY 2.7 Configuration of Analog and Digital Pins During ICSP Operations If an ICSP compliant emulator is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as “digital” pins. Depending on the particular device, this is done by setting all bits in the ADnPCFG register(s), or clearing all bit in the ANSx registers. All PIC24F devices will have either one or more ADnPCFG registers or several ANSx registers (one for each port); no device will have both.
PIC24FJ64GA104 FAMILY NOTES: DS39951C-page 24 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY 3.0 Note: CPU This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 2. “CPU” (DS39703). The PIC24F CPU has a 16-bit (data), modified Harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field.
PIC24FJ64GA104 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 23 PCH PCL Program Counter Loop Stack Control Control Logic Logic 16 Data RAM Address Latch 23 16 RAGU WAGU Address Latch Program Memory EA MUX Address Bus Data Latch ROM Latch 24 Control Signals to Various Blocks Instruction Reg Hardware Multiplier Divide Support 16 Literal Data Instruction Decode & Control 16 16 x 16 W Register
PIC24FJ64GA104 FAMILY TABLE 3-1: CPU CORE REGISTERS Register(s) Name Description W0 through W15 Working Register Array PC 23-Bit Program Counter SR ALU STATUS Register SPLIM Stack Pointer Limit Value Register TBLPAG Table Memory Page Address Register PSVPAG Program Space Visibility Page Address Register RCOUNT Repeat Loop Counter Register CORCON CPU Control Register FIGURE 3-2: PROGRAMMER’S MODEL 15 Divider Working Registers 0 W0 (WREG) W1 W2 Multiplier Registers W3 W4 W5 W6 W7 Wo
PIC24FJ64GA104 FAMILY 3.
PIC24FJ64GA104 FAMILY REGISTER 3-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — U-0 — — U-0 R/C-0 (1) — IPL3 R/W-0 U-0 U-0 PSV — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU interrupt prio
PIC24FJ64GA104 FAMILY 3.3.2 DIVIDER 3.3.3 The divide block supports signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1.
PIC24FJ64GA104 FAMILY 4.0 MEMORY ORGANIZATION As Harvard architecture devices, PIC24F microcontrollers feature separate program and data memory spaces and busses. This architecture also allows the direct access of program memory from the data space during code execution. 4.1 Program Address Space The program address memory space of the PIC24FJ64GA104 family devices is 4M instructions.
PIC24FJ64GA104 FAMILY 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.3 In PIC24FJ64GA104 family devices, the top four words of on-chip program memory are reserved for configuration information. On device Reset, the configuration information is copied into the appropriate Configuration registers. The addresses of the Flash Configuration Word for devices in the PIC24FJ64GA104 family are shown in Table 4-1. Their location in the memory map is shown with the other memory vectors in Figure 4-1.
PIC24FJ64GA104 FAMILY 4.2 Data Address Space The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range. The data space is accessed using two Address Generation Units (AGUs), one each for read and write operations. The data space memory map is shown in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This gives a data space address range of 64 Kbytes or 32K words.
PIC24FJ64GA104 FAMILY 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT A Sign-Extend (SE) instruction is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a Zero-Extend (ZE) instruction on the appropriate address. To maintain backward compatibility with PIC® devices and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations.
2010 Microchip Technology Inc.
ICN REGISTER MAP File Addr Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE(1) CN9IE(1) CN27IE (1) CNEN2 0062 — Legend: Note 1: — Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets CN8IE(1) CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 CN24IE CN23IE CN22IE CN21IE CN20IE(1) CN19IE(1) CN18IE(1) CN17IE(1) CN16IE 0000 CN11PUE CN10PUE(1) CN9PUE(1) CN8PUE(1) CN7PUE CN6PUE CN5PUE CN4PUE C
2010 Microchip Technology Inc.
File Name Addr TIMER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 TMR1 0100 Timer1 Register PR1 0102 Timer1 Period Register T1CON 0104 TON — TSIDL — — — — — — Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 FFFF TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 TMR2 0106 Timer2 Register 0000 TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) 0000 TMR3 010A Timer3 Register 0000 PR2 010C Timer2 Period Reg
2010 Microchip Technology Inc.
File Name Addr OUTPUT COMPARE REGISTER MAP Bit 15 Bit 14 Bit 13 — OCSIDL Bit 12 Bit 11 Bit 10 Bit 8 ENFLT2 ENFLT1 DCB0 OC32 Bit 7 Bit 6 Bit 5 ENFLT0 OCFLT2 OCFLT1 OCTRIG TRIGSTAT OCTRIS Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 OC1CON1 0190 — OC1CON2 0192 FLTMD OC1RS 0194 Output Compare 1 Secondary Register 0000 OC1R 0196 Output Compare 1 Register 0000 OC1TMR 0198 Timer Value 1 Register OC2CON1 019A — OC2CON2 019C F
2010 Microchip Technology Inc.
File Name SPI REGISTER MAPS Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 SPIBEC2 SPIBEC1 SPIBEC0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 SPI1STAT 0240 SPIEN — SPISIDL — — SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 SPI1CON2 0244 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN 0000
2010 Microchip Technology Inc. TABLE 4-15: File Name PAD CONFIGURATION REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PADCFG1 02FC — — — — — — — — — — — — — Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File Name Addr PARALLEL MASTER/SLAVE PORT REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 PMCON 0600 PMPEN — PSIDL PMMODE 0602 BUSY IRQM1 IRQM0 INCM1 INCM0 PMADDR 0604 — CS1 — — — Bit 10 ADRMUX1 ADRMUX0 Bit 9 PTBEEN Bit 8 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 CSF1 CSF0 ALP — CS1P BEP WRSP RDSP WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0 0000 ADDR10(1) ADDR9(1) ADDR8(1) ADDR7(1) ADDR6(1) ADDR5(1) ADDR4(1) ADDR3(1) ADDR2(1)
2010 Microchip Technology Inc.
SYSTEM REGISTER MAP File Name Addr Bit 15 Bit 14 RCON 0740 TRAPR IOPUWR OSCCON 0742 — COSC2 CLKDIV 0744 ROI DOZE2 OSCTUN 0748 — — REFOCON 074E ROEN — Legend: Note 1: 2: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. The Reset value of the RCON register is dependent on the type of Reset event. See Section 6.0 “Resets” for more information. The Reset value of the OSCCON register is dependent on both the type of Reset event and the device configuration.
PIC24FJ64GA104 FAMILY 4.2.5 4.3 SOFTWARE STACK In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown in Figure 4-4. Note that for a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear.
PIC24FJ64GA104 FAMILY TABLE 4-27: PROGRAM SPACE ADDRESS CONSTRUCTION Program Space Address Access Space <23> Instruction Access (Code Execution) User 0 TBLRD/TBLWT (Byte/Word Read/Write) User TBLPAG<7:0> Data EA<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx Access Type <15> <14:1> <0> PC<22:1> 0 0xx xxxx xxxx xxxx xxxx xxx0 Program Space Visibility (Block Remap/Read) Note 1: <22:16> User 0 PSVPAG<7:0> Data EA<14:0>(1)
PIC24FJ64GA104 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word.
PIC24FJ64GA104 FAMILY 4.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H).
PIC24FJ64GA104 FAMILY 5.0 Note: FLASH PROGRAM MEMORY RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instructions (192 bytes) at a time and erase program memory in blocks of 512 instructions (1536 bytes) at a time. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24FJ64GA104 FAMILY 5.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions) at a time and to program one row at a time. It is also possible to program single words. The 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively.
PIC24FJ64GA104 FAMILY REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0, HC(1) R/W-0(1) R/W-0, HS(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 U-0 R/W-0(1) U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) — ERASE — — NVMOP3(2) NVMOP2(2) NVMOP1(2) NVMOP0(2) bit 7 bit 0 Legend: SO = Settable Only bit HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ =
PIC24FJ64GA104 FAMILY 5.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. The user can program one row of Flash program memory at a time. To do this, it is necessary to erase the 8-row erase block containing the desired row. The general process is as follows: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data.
PIC24FJ64GA104 FAMILY EXAMPLE 5-2: ERASING A PROGRAM MEMORY BLOCK (C LANGUAGE CODE) // C example using MPLAB C30 unsigned long progAddr = 0xXXXXXX; unsigned int offset; // Address of row to write //Set up pointer to the first memory location to be written TBLPAG = progAddr>>16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase block // with dummy latch write NVMCON = 0x4042; // Initialize N
PIC24FJ64GA104 FAMILY EXAMPLE 5-4: LOADING THE WRITE BUFFERS (C LANGUAGE CODE) // C example using MPLAB C30 #define NUM_INSTRUCTION_PER_ROW 64 unsigned int offset; unsigned int i; unsigned long progAddr = 0xXXXXXX; unsigned int progData[2*NUM_INSTRUCTION_PER_ROW]; //Set up NVMCON for row programming NVMCON = 0x4001; // Address of row to write // Buffer of data to write // Initialize NVMCON //Set up pointer to the first memory location to be written TBLPAG = progAddr>>16; // Initialize PM Page Boundary
PIC24FJ64GA104 FAMILY 5.6.2 PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY instructions write the desired data into the write latches and specify the lower 16 bits of the program memory address to write to. To configure the NVMCON register for a word write, set the NVMOP bits (NVMCON<3:0>) to ‘0011’. The write is performed by executing the unlock sequence and setting the WR bit (see Example 5-7).
PIC24FJ64GA104 FAMILY NOTES: DS39951C-page 58 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY 6.0 Note: RESETS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 7. “Reset” (DS39712). The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST.
PIC24FJ64GA104 FAMILY RCON: RESET CONTROL REGISTER(1) REGISTER 6-1: R/W-0 TRAPR bit 15 R/W-0 IOPUWR U-0 — U-0 — U-0 — R/CO-0, HS DPSLP R/W-0 CM R/W-0 PMSLP bit 8 R/W-0 EXTR bit 7 R/W-0 SWR R/W-0 SWDTEN(2) R/W-0 WDTO R/W-0, SLEEP R/W-0 IDLE R/W-1 BOR R/W-1 POR bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13-11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 Note 1: 2: CO = Clearable Only bit W = Writable bit ‘1’ = Bit is set HS = Hardware Settable bi
PIC24FJ64GA104 FAMILY RCON: RESET CONTROL REGISTER(1) (CONTINUED) REGISTER 6-1: bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred. Note that BOR is also set after a Power-on Reset. 0 = A Brown-out Reset has not occurred POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred bit 0 Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset.
PIC24FJ64GA104 FAMILY TABLE 6-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Reset Type POR(6) EC BOR All Others Note 1: 2: 3: 4: 5: 6: Clock Source SYSRST Delay System Clock Delay TPOR + TRST + TPWRT — Notes 1, 2, 3, 8 FRC, FRCDIV TPOR + TRST + TPWRT TFRC 1, 2, 3, 4, 7, 8 LPRC TPOR + TRST + TPWRT TLPRC 1, 2, 3, 4, 8 1, 2, 3, 5, 8 ECPLL TPOR + TRST + TPWRT TLOCK FRCPLL TPOR + TRST + TPWRT TFRC + TLOCK XT, HS, SOSC TPOR+ TRST + TPWRT TOST XTPLL, HSPLL TPOR + TRST + TPWRT TOST +
PIC24FJ64GA104 FAMILY 6.2.1 POR AND LONG OSCILLATOR START-UP TIMES The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: • The oscillator circuit has not begun to oscillate.
PIC24FJ64GA104 FAMILY NOTES: DS39951C-page 64 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY 7.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 8. “Interrupts” (DS39707). The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the PIC24F CPU.
PIC24FJ64GA104 FAMILY FIGURE 7-1: PIC24F INTERRUPT VECTOR TABLE Decreasing Natural Order Priority Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — — — Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 — — — Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Ve
PIC24FJ64GA104 FAMILY TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Bit Locations Vector Number IVT Address AIVT Address Flag Enable ADC1 Conversion Done 13 00002Eh 00012Eh IFS0<13> IEC0<13> IPC3<6:4> Comparator Event 18 000038h 000138h IFS1<2> IEC1<2> IPC4<10:8> CRC Generator 67 00009Ah 00019Ah IFS4<3> IEC4<3> IPC16<14:12> CTMU Event 77 0000AEh 0001AEh IFS4<13> IEC4<13> IPC19<6:4> Interrupt Source Priority External Interrupt 0 0 000014h 000114h IFS0<0> IEC0<0>
PIC24FJ64GA104 FAMILY 7.3 Interrupt Control and Status Registers The PIC24FJ64GA104 family of devices implements the following registers for the interrupt controller: • • • • • INTCON1 INTCON2 IFS0 through IFS4 IEC0 through IEC4 IPC0 through IPC20 (except IPC13, IPC14 and IPC17) • INTTREG Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the processor trap sources.
PIC24FJ64GA104 FAMILY REGISTER 7-1: SR: ALU STATUS REGISTER (IN CPU) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0 — — — — — — — DC(1) bit 15 bit 8 R/W-0 IPL2 (2,3) R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU
PIC24FJ64GA104 FAMILY REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting
PIC24FJ64GA104 FAMILY REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use Alternate Interrupt Vector Table 0 = Use
PIC24FJ64GA104 FAMILY REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 — bit 15 U-0 — R/W-0 AD1IF R/W-0 U1TXIF R/W-0 U1RXIF R/W-0 SPI1IF R/W-0 SPF1IF R/W-0 T3IF bit 8 R/W-0 T2IF bit 7 R/W-0 OC2IF R/W-0 IC2IF U-0 — R/W-0 T1IF R/W-0 OC1IF R/W-0 IC1IF R/W-0 INT0IF bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read a
PIC24FJ64GA104 FAMILY REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 =
PIC24FJ64GA104 FAMILY REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 — — PMPIF — — — OC5IF — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF — — — SPI2IF SPF2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 PMPIF: Parallel Master Port Interrupt Flag Statu
PIC24FJ64GA104 FAMILY REGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — RTCIF — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0, R/W-0 U-0 — — — — — MI2C2IF SI2C2IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit 1 = Interrupt
PIC24FJ64GA104 FAMILY REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIF — — — — LVDIF bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIF U2ERIF U1ERIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIF: CTMU Interrupt Flag Status bit 1 = Interrupt reques
PIC24FJ64GA104 FAMILY REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 — bit 15 U-0 — R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPF1IE R/W-0 T3IE bit 8 R/W-0 T2IE bit 7 R/W-0 OC2IE R/W-0 IC2IE U-0 — R/W-0 T1IE R/W-0 OC1IE R/W-0 IC1IE R/W-0 INT0IE bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, re
PIC24FJ64GA104 FAMILY REGISTER 7-11: R/W-0 U2TXIE bit 15 IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 U2RXIE R/W-0 INT2IE(1) R/W-0 T5IE R/W-0 T4IE U-0 — U-0 — R/W-0 INT1IE(1) R/W-0 CNIE bit 7 Legend: R = Readable bit -n = Value at POR bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8-5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: R/W-0 OC3IE U-0 — bit 8 U-0 — bit 15 R/W-0 OC4IE W = Writable bit ‘1’ = Bit is set R/W-0 CMIE R/W-0 MI2C1IE R/W-0 SI2C1IE bit 0 U = Unimplemented bit, read
PIC24FJ64GA104 FAMILY REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 — — PMPIE — — — OC5IE — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 IC5IE IC4IE IC3IE — — — SPI2IE SPF2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 PMPIE: Parallel Master Port Interrupt Enable
PIC24FJ64GA104 FAMILY REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — RTCIE — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — MI2C2IE SI2C2IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit 1 = Interrupt re
PIC24FJ64GA104 FAMILY REGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIE — — — — LVDIE bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIE U2ERIE U1ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt request
PIC24FJ64GA104 FAMILY REGISTER 7-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1
PIC24FJ64GA104 FAMILY REGISTER 7-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC2IP2 IC2IP1 IC2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrup
PIC24FJ64GA104 FAMILY REGISTER 7-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-
PIC24FJ64GA104 FAMILY REGISTER 7-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP<2:0>: A/D Conversion Complete Inter
PIC24FJ64GA104 FAMILY REGISTER 7-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-
PIC24FJ64GA104 FAMILY REGISTER 7-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrup
PIC24FJ64GA104 FAMILY REGISTER 7-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — OC3IP2 OC3IP1 OC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interrup
PIC24FJ64GA104 FAMILY REGISTER 7-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-
PIC24FJ64GA104 FAMILY REGISTER 7-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Prio
PIC24FJ64GA104 FAMILY REGISTER 7-24: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC3IP2 IC3IP1 IC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC5IP<2:0>: Input Captu
PIC24FJ64GA104 FAMILY REGISTER 7-25: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — OC5IP2 OC5IP1 OC5IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 OC5IP<2:0>: Output Compare Channel 5 Interrupt Priority bits 11
PIC24FJ64GA104 FAMILY REGISTER 7-26: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — PMPIP2 PMPIP1 PMPIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PMPIP<2:0>: Parallel Master Port Interrupt Priority bits 111 =
PIC24FJ64GA104 FAMILY REGISTER 7-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 MI2C2IP<2:0>: Master I2C2 Ev
PIC24FJ64GA104 FAMILY REGISTER 7-28: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — RTCIP2 RTCIP1 RTCIP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP<2:0>: Real-Time Clock/Calendar Interrupt Priority bits
PIC24FJ64GA104 FAMILY REGISTER 7-29: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP<2:0>: CRC
PIC24FJ64GA104 FAMILY REGISTER 7-30: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — LVDIP2 LVDIP1 LVDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 LVDIP<2:0>: Low-Voltage Detect Interrupt Priority bits 111 = In
PIC24FJ64GA104 FAMILY REGISTER 7-32: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER R-0 U-0 R/W-0 U-0 R-0 R-0 R-0 R-0 CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CPUIRQ: Interrupt Request from Interr
PIC24FJ64GA104 FAMILY 7.4 Interrupt Setup Procedures 7.4.1 INITIALIZATION To configure an interrupt source: 1. 2. Set the NSTDIS control bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source.
PIC24FJ64GA104 FAMILY NOTES: DS39951C-page 100 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY 8.0 OSCILLATOR CONFIGURATION Note: • Software-controllable switching between various clock sources • Software-controllable postscaler for selective clocking of CPU for system power savings • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown • A separate and independently configurable system clock output for synchronizing external hardware This data sheet summarizes the features of this group of PIC24F devices.
PIC24FJ64GA104 FAMILY 8.1 CPU Clocking Scheme 8.2 The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins • Fast Internal RC (FRC) Oscillator • Low-Power Internal RC (LPRC) Oscillator The Primary Oscillator and FRC sources have the option of using the internal 4x PLL. The frequency of the FRC clock source can optionally be reduced by the programmable clock divider.
PIC24FJ64GA104 FAMILY 8.3 Control Registers The operation of the oscillator is controlled by three Special Function Registers: • OSCCON • CLKDIV • OSCTUN The OSCCON register (Register 8-1) is the main control register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. REGISTER 8-1: The CLKDIV register (Register 8-2) controls the features associated with Doze mode, as well as the postscaler for the FRC Oscillator.
PIC24FJ64GA104 FAMILY REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
PIC24FJ64GA104 FAMILY REGISTER 8-2: R/W-0 CLKDIV: CLOCK DIVIDER REGISTER R/W-0 ROI R/W-0 DOZE2 DOZE1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit and
PIC24FJ64GA104 FAMILY REGISTER 8-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TUN5(1) TUN4(1) TUN3(1) TUN2(1) TUN1(1) TUN0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tu
PIC24FJ64GA104 FAMILY 8.4.2 OSCILLATOR SWITCHING SEQUENCE A recommended code sequence for a clock switch includes the following: At a minimum, performing a clock switch requires this basic sequence: 1. 1. 2. 2. 3. 4. 5. If desired, read the COSCx bits (OSCCON<14:12>), to determine the current oscillator source. Perform the unlock sequence to allow a write to the OSCCON register high byte. Write the appropriate value to the NOSCx bits (OSCCON<10:8>) for the new oscillator source.
PIC24FJ64GA104 FAMILY 8.5 8.5.1 Secondary Oscillator (SOSC) BASIC SOSC OPERATION PIC24FJ64GA104 family devices do not have to set the SOSCEN bit to use the Secondary Oscillator. Any module requiring the SOSC (such as RTCC, Timer1 or DSWDT) will automatically turn on the SOSC when the clock signal is needed. The SOSC, however, has a long start-up time. To avoid delays for peripheral start-up, the SOSC can be manually started using the SOSCEN bit.
PIC24FJ64GA104 FAMILY REGISTER 8-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Referenc
PIC24FJ64GA104 FAMILY NOTES: DS39951C-page 110 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY 9.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 39. “Power-Saving Features with Deep Sleep” (DS39727). The PIC24FJ64GA104 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals.
PIC24FJ64GA104 FAMILY 9.2.2 IDLE MODE Note: Idle mode has these features: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “Selective Peripheral Module Control”). • If the WDT or FSCM is enabled, the LPRC will also remain active.
PIC24FJ64GA104 FAMILY 9.2.4.2 Special Cases when Entering Deep Sleep Mode When entering Deep Sleep mode, there are certain circumstances that require a delay between setting the DSEN bit and executing the PWRSAV instruction. These can be generally reduced to three scenarios: 1. 2. 3.
PIC24FJ64GA104 FAMILY 9.2.4.3 Exiting Deep Sleep Mode Deep Sleep mode exits on any one of the following events: • POR event on VDD supply. If there is no DSBOR circuit to re-arm the VDD supply POR circuit, the external VDD supply must be lowered to the natural arming voltage of the POR circuit. • DSWDT time-out. When the DSWDT timer times out, the device exits Deep Sleep. • RTCC alarm (if RTCEN = 1). • Assertion (‘0’) of the MCLR pin.
PIC24FJ64GA104 FAMILY Once the device wakes back up, all I/O pins continue to maintain their previous states, even after the device has finished the POR sequence and is executing application code again. Pins configured as inputs during Deep Sleep remain high-impedance and pins configured as outputs continue to drive their previous value. After waking up, the TRIS and LAT registers, and the SOSCEN bit (OSCCON<1>) are reset.
PIC24FJ64GA104 FAMILY 9.2.4.10 Power-on Resets (PORs) 9.2.4.11 Summary of Deep Sleep Sequence VDD voltage is monitored to produce PORs. Since exiting from Deep Sleep functionally looks like a POR, the technique described in Section 9.2.4.9 “Checking and Clearing the Status of Deep Sleep” should be used to distinguish between Deep Sleep and a true POR event.
PIC24FJ64GA104 FAMILY REGISTER 9-1: DSCON: DEEP SLEEP CONTROL REGISTER R/W-0, HC U-0 U-0 U-0 U-0 U-0 U-0 U-0 DSEN(1) — — — — — — — bit 15 bit 8 U-0 U-0 — — U-0 — U-0 — U-0 — U-0 — R/W-0, HCS R/C-0, HS (1,2,3) RELEASE(1,2) DSBOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit C = Clearable bit U = Unimplemented, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HC = Hardware Clearable bit HS = Hardware Settable bit HCS =
PIC24FJ64GA104 FAMILY REGISTER 9-2: DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS — — — — — — — DSINT0(1) bit 15 bit 8 R/W-0, HS DSFLT U-0 (1) — U-0 — R/W-0, HS R/W-0, HS R/W-0, HS (1) (1) (1) DSWDT DSRTC U-0 R/W-0, HS — DSPOR(2) DSMCLR bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC24FJ64GA104 FAMILY 9.3 Doze Mode Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. There may be circumstances, however, where this is not practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else.
PIC24FJ64GA104 FAMILY NOTES: DS39951C-page 120 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY 10.0 Note: I/O PORTS When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port. This data sheet summarizes the features of this group of PIC24F devices.
PIC24FJ64GA104 FAMILY 10.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g.
PIC24FJ64GA104 FAMILY 10.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24FJ64GA104 family of devices to generate interrupt requests to the processor in response to a Change-of-State (COS) on selected input pins. This feature is capable of detecting input Change-of-States even in Sleep mode, when the clocks are disabled.
PIC24FJ64GA104 FAMILY 10.4.3 CONTROLLING PERIPHERAL PIN SELECT Peripheral Pin Select features are controlled through two sets of Special Function Registers: one to map peripheral inputs and one to map outputs. Because they are separately controlled, a particular peripheral’s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint.
PIC24FJ64GA104 FAMILY 10.4.3.2 Output Mapping the bit field corresponds to one of the peripherals and that peripheral’s output is mapped to the pin (see Table 10-3). In contrast to inputs, the outputs of the Peripheral Pin Select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping.
PIC24FJ64GA104 FAMILY 10.4.3.3 Mapping Limitations The control schema of the Peripheral Pin Select is extremely flexible. Other than systematic blocks that prevent signal contention caused by two physical pins being configured as the same functional input, or two functional outputs configured as the same pin, there are no hardware enforced lock outs. The flexibility extends to the point of allowing a single input to drive multiple peripherals or a single functional output to drive multiple output pins.
PIC24FJ64GA104 FAMILY 10.4.5 CONSIDERATIONS FOR PERIPHERAL PIN SELECTION The ability to control Peripheral Pin Selection introduces several considerations into application design that could be overlooked. This is particularly true for several common peripherals that are available only as remappable peripherals. The main consideration is that the Peripheral Pin Selects are not available on default pins in the device’s default (Reset) state.
PIC24FJ64GA104 FAMILY EXAMPLE 10-2: ;unlock push push push mov mov mov mov.b mov.b bclr CONFIGURING UART1 INPUT AND OUTPUT FUNCTIONS IN ASSEMBLY CODE registers w1; w2; w3; #OSCCON, w1; #0x46, w2; #0x57, w3; w2, [w1]; w3, [w1]; OSCCON, #6; ; Configure Input Functions (Table10-2) ; Assign U1CTS To Pin RP1, U1RX To Pin RP0 mov #0x0100, w1; mov w1,RPINR18; ; Configure Output Functions (Table 10-3) ; Assign U1RTS To Pin RP3, U1TX To Pin RP2 mov #0x0403, w1; mov w1, RPOR1; ;lock mov mov mov mov.b mov.
PIC24FJ64GA104 FAMILY 10.4.6 PERIPHERAL PIN SELECT REGISTERS Note: The PIC24FJ64GA104 family of devices implements a total of 27 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (14) • Output Remappable Peripheral Registers (13) REGISTER 10-1: Input and output register values can only be changed if IOLOCK (OSCCON<6>) = 0. See Section 10.4.4.1 “Control Register Lock” for a specific command sequence.
PIC24FJ64GA104 FAMILY REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T2CKR4 T2CKR3 T2CKR2 T2CKR1 T2CKR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ b
PIC24FJ64GA104 FAMILY REGISTER 10-5: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 I
PIC24FJ64GA104 FAMILY REGISTER 10-7: RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC5R4 IC5R3 IC5R2 IC5R1 IC5R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 IC5R<4:0>: Assign Input Capture 5
PIC24FJ64GA104 FAMILY REGISTER 10-9: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as
PIC24FJ64GA104 FAMILY REGISTER 10-11: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’
PIC24FJ64GA104 FAMILY REGISTER 10-13: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’
PIC24FJ64GA104 FAMILY REGISTER 10-15: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP
PIC24FJ64GA104 FAMILY REGISTER 10-17: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP5R4 RP5R3 RP5R2 RP5R1 RP5R0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP4R4 RP4R3 RP4R2 RP4R1 RP4R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP
PIC24FJ64GA104 FAMILY REGISTER 10-19: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP8R4 RP8R3 RP8R2 RP8R1 RP8R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP
PIC24FJ64GA104 FAMILY REGISTER 10-21: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bi
PIC24FJ64GA104 FAMILY REGISTER 10-23: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP17R4 RP17R3 RP17R2 RP17R1 RP17R0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP16R4 RP16R3 RP16R2 RP16R1 RP16R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’
PIC24FJ64GA104 FAMILY REGISTER 10-25: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP21R4 RP21R3 RP21R2 RP21R1 RP21R0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0
PIC24FJ64GA104 FAMILY REGISTER 10-27: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP25R4 RP25R3 RP25R2 RP25R1 RP25R0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP24R4 RP24R3 RP24R2 RP24R1 RP24R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0
PIC24FJ64GA104 FAMILY 11.0 Note: TIMER1 Figure 11-1 presents a block diagram of the 16-bit timer module. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 14. “Timers” (DS39704). To configure Timer1 for operation: 1. 2. 3.
PIC24FJ64GA104 FAMILY REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER(1) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Rea
PIC24FJ64GA104 FAMILY 12.0 Note: TIMER2/3 AND TIMER4/5 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 14. “Timers” (DS39704). The Timer2/3 and Timer4/5 modules are 32-bit timers, which can also be configured as four independent 16-bit timers with selectable operating modes. To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. 2. 3. 4.
PIC24FJ64GA104 FAMILY FIGURE 12-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM TCKPS<1:0> 2 TON T2CK (T4CK) 1x Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 TGATE(2) TGATE TCS(2) Q 1 Set T3IF (T5IF) Q 0 PR3 (PR5) ADC Event Trigger(3) Equal D CK PR2 (PR4) Comparator MSB LSB TMR3 (TMR5) Reset TMR2 (TMR4) Sync 16 Read TMR2 (TMR4) (1) Write TMR2 (TMR4)(1) 16 TMR3HLD (TMR5HLD) 16 Data Bus<15:0> Note 1: 2: 3: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counte
PIC24FJ64GA104 FAMILY FIGURE 12-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM TON T2CK (T4CK) TCKPS<1:0> 2 1x Gate Sync Prescaler 1, 8, 64, 256 01 00 TGATE TCS(1) TCY 1 Set T2IF (T4IF) 0 Reset Equal Q D Q CK TMR2 (TMR4) TGATE(1) Sync Comparator PR2 (PR4) Note 1: The timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Pin Select (PPS)” for more information.
PIC24FJ64GA104 FAMILY REGISTER 12-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(3) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 T32(1) — TCS(2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timerx On bit When TxCON<3> = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-bi
PIC24FJ64GA104 FAMILY REGISTER 12-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER(3) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(1) TCKPS1(1) TCKPS0(1) — — TCS(1,2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery
PIC24FJ64GA104 FAMILY NOTES: DS39951C-page 150 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY 13.0 INPUT CAPTURE WITH DEDICATED TIMERS Note: 13.1 13.1.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 34. “Input Capture with Dedicated Timer” (DS39722). Devices in the PIC24FJ64GA104 family all feature 5 independent input capture modules.
PIC24FJ64GA104 FAMILY 13.1.2 CASCADED (32-BIT) MODE By default, each module operates independently with its own 16-bit timer. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, modules 1 and 2 are paired, as are modules 3 and 4, and so on.) The odd-numbered module (ICx) provides the Least Significant 16 bits of the 32-bit register pairs, and the even module (ICy) provides the Most Significant 16 bits.
PIC24FJ64GA104 FAMILY REGISTER 13-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — bit 15 bit 8 U-0 R/W-0 R/W-0 R-0, HCS R-0, HCS R/W-0 R/W-0 R/W-0 — ICI1 ICI0 ICOV ICBNE ICM2(1) ICM1(1) ICM0(1) bit 7 bit 0 Legend: HCS = Hardware Clearable/Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is
PIC24FJ64GA104 FAMILY REGISTER 13-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — IC32 bit 15 bit 8 R/W-0 R/W-0, HS U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unim
PIC24FJ64GA104 FAMILY 14.0 Note: OUTPUT COMPARE WITH DEDICATED TIMERS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 35. “Output Capture with Dedicated Timer” (DS39723). All devices in the PIC24FJ64GA104 family features 5 independent output compare modules.
PIC24FJ64GA104 FAMILY FIGURE 14-1: OUTPUT COMPARE BLOCK DIAGRAM (16-BIT MODE) DCBx OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLTx OCFLTx OCxCON1 OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG Clock Select OC Clock Sources OCxCON2 OCxR Increment Comparator OC Output and Fault Logic OCxTMR Reset Match Event Trigger and Sync Sources Trigger and Sync Logic Comparator OCx Pin(1) Match Event Match Event OCFA/ OCFB/ CxOUT OCxRS Reset OCx Interrupt Note 1: The OCx outputs must be assigned to an avai
PIC24FJ64GA104 FAMILY 14.2 Compare Operations In Compare mode (Figure 14-1), the output compare module can be configured for single-shot or continuous pulse generation; it can also repeatedly toggle an output pin on each timer event. To set up the module for compare operations: 1. 2. 3. 4. 5. 6. 7. Configure the OCx output for one of the available Peripheral Pin Select pins.
PIC24FJ64GA104 FAMILY 14.3 Pulse-Width Modulation (PWM) Mode 5. 6. In PWM mode, the output compare module can be configured for edge-aligned or center-aligned pulse waveform generation. All PWM operations are double-buffered (buffer registers are internal to the module and are not mapped into SFR space). To configure the output compare edge-aligned PWM operation: 1. 2. 3. 4. module 7. 8. for Note: Configure the OCx output for one of the available Peripheral Pin Select pins.
PIC24FJ64GA104 FAMILY 14.3.1 PWM PERIOD 14.3.2 PWM DUTY CYCLE In edge aligned PWM mode, the period is specified by the value of OCxRS register. In center aligned PWM mode, the period of the synchronization source such as Timer's PRy specifies the period. The period in both cases can be calculated using Equation 14-1. The PWM duty cycle is specified by writing to the OCxRS and OCxR registers.
PIC24FJ64GA104 FAMILY 14.4 Subcycle Resolution The DCB bits are intended for use with a clock source identical to the system clock. When an OCx module with enabled prescaler is used, the falling edge delay caused by the DCB bits will be referenced to the system clock period, rather than the OCx module's period. The DCB bits (OCxCON2<10:9>) provide for resolution better than one instruction cycle. When used, they delay the falling edge generated by a match event by a portion of an instruction cycle.
PIC24FJ64GA104 FAMILY REGISTER 14-1: U-0 OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 U-0 — R/W-0 — R/W-0 OCSIDL OCTSEL2 R/W-0 OCTSEL1 R/W-0 OCTSEL0 R/W-0 ENFLT2 (2) R/W-0 ENFLT1 bit 15 bit 8 R/W-0 R/W-0, HCS R/W-0, HCS R/W-0, HCS R/W-0 R/W-0 R/W-0 R/W-0 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2(1) OCM1(1) OCM0(1) bit 7 bit 0 Legend: HCS = Hardware Clearable/Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is
PIC24FJ64GA104 FAMILY REGISTER 14-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED) OCM<2:0>: Output Compare x Mode Select bits(1) 111 = Center-Aligned PWM mode on OCx 110 = Edge-Aligned PWM mode on OCx 101 = Double Compare Continuous Pulse mode: initialize OCx pin low, toggle OCx state continuously on alternate matches of OCxR and OCxRS 100 = Double Compare Single-Shot mode: initialize OCx pin low, toggle OCx state on matches of OCxR and OCxRS for one cycle 011 = Single Compare Continuous Pulse
PIC24FJ64GA104 FAMILY REGISTER 14-2: R/W-0 OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 R/W-0 FLTMD R/W-0 FLTOUT R/W-0 FLTTRIEN U-0 R/W-0 — OCINV DCB1 (3) R/W-0 DCB0 R/W-0 (3) OC32 bit 15 bit 8 R/W-0 R/W-0, HS R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0
PIC24FJ64GA104 FAMILY REGISTER 14-2: bit 4-0 OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED) SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits 11111 = This OC module(1) 11110 = Reserved 11101 = Reserved 11100 = CTMU(2) 11011 = A/D(2) 11010 = Comparator 3(2) 11001 = Comparator 2(2) 11000 = Comparator 1(2) 10111 = Input Capture 4(2) 10110 = Input Capture 3(2) 10101 = Input Capture 2(2) 10100 = Input Capture 1(2) 100xx = Reserved 01111 = Timer5 01110 = Timer4 01101 = Timer3 01100 = Timer2
PIC24FJ64GA104 FAMILY 15.0 Note: SERIAL PERIPHERAL INTERFACE (SPI) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 23. “Serial Peripheral Interface (SPI)” (DS39699). The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices.
PIC24FJ64GA104 FAMILY To set up the SPI module for the Standard Master mode of operation: To set up the SPI module for the Standard Slave mode of operation: 1. 1. 2. 2. 3. 4. 5. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register to set the interrupt priority. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 1.
PIC24FJ64GA104 FAMILY To set up the SPI module for the Enhanced Buffer Master mode of operation: To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. 1. 2. 2. 3. 4. 5. 6. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 1.
PIC24FJ64GA104 FAMILY REGISTER 15-1: R/W-0 SPIEN (1) SPIxSTAT: SPIx STATUS AND CONTROL REGISTER U-0 R/W-0 U-0 U-0 R-0 R-0 R-0 — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 bit 15 bit 8 R-0 R/C-0, HS R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
PIC24FJ64GA104 FAMILY REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED) bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started; SPIxTXB is full 0 = Transmit started; SPIxTXB is empty In Standard Buffer mode: Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.
PIC24FJ64GA104 FAMILY REGISTER 15-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK(1) DISSDO(2) MODE16 SMP CKE(3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 (4) SSEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0
PIC24FJ64GA104 FAMILY REGISTER 15-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 ... 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: 2: 3: 4: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 10.
PIC24FJ64GA104 FAMILY FIGURE 15-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE) PROCESSOR 1 (SPI Master) PROCESSOR 2 (SPI Slave) SDIx SDOx Serial Receive Buffer (SPIxRXB) Serial Receive Buffer (SPIxRXB) SDOx SDIx Shift Register (SPIxSR) LSb MSb MSb Serial Transmit Buffer (SPIxTXB) SPIx Buffer (SPIxBUF)(2) Shift Register (SPIxSR) LSb Serial Transmit Buffer (SPIxTXB) SCKx Serial Clock SCKx SPIx Buffer (SPIxBUF)(2) SSx(1) SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0 MSTEN (SPIxCON1<5>
PIC24FJ64GA104 FAMILY FIGURE 15-5: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Master, Frame Master) PROCESSOR 2 SDIx SDOx SDOx SDIx SCKx SSx FIGURE 15-6: Serial Clock Frame Sync Pulse SCKx SSx SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM PIC24F SPI Master, Frame Slave) PROCESSOR 2 SDOx SDIx SDIx SDOx SCKx SSx FIGURE 15-7: Serial Clock Frame Sync Pulse SCKx SSx SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Master) PROCESSOR 2 SDOx SDIx SDIx SDOx SCK
PIC24FJ64GA104 FAMILY EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1) FSCK = FCY Primary Prescaler * Secondary Prescaler Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
PIC24FJ64GA104 FAMILY 16.0 Note: INTER-INTEGRATED CIRCUIT (I2C™) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 24. “Inter-Integrated Circuit™ (I2C™)” (DS39702). The Inter-Integrated Circuit (I2C) module is a serial interface useful for communicating with other peripheral or microcontroller devices.
PIC24FJ64GA104 FAMILY FIGURE 16-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2CxRCV SCLx Read Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read TCY/2 DS39951C-page 176 2010 Microchip Technolo
PIC24FJ64GA104 FAMILY 16.2 Setting Baud Rate When Operating as a Bus Master 16.3 The I2CxMSK register (Register 16-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2CxMSK register causes the slave module to respond whether the corresponding address bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK is set to ‘00100000’, the slave module will detect both addresses: ‘0000000’ and ‘0100000’.
PIC24FJ64GA104 FAMILY REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bi
PIC24FJ64GA104 FAMILY REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (When operating as I2C master. Applicable during master receive.) Value that will be transmitted when the software initiates an Acknowledge sequence. 1 = Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (When operating as I2C master. Applicable during master receive.
PIC24FJ64GA104 FAMILY REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC IWCOL I2COV D/A P R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC S R/W RBF TBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at
PIC24FJ64GA104 FAMILY REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop is detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop is detected.
PIC24FJ64GA104 FAMILY REGISTER 16-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AM
PIC24FJ64GA104 FAMILY 17.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 21. “UART” (DS39708). The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the PIC24F device family.
PIC24FJ64GA104 FAMILY 17.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator. The UxBRG register controls the period of a free-running, 16-bit timer. Equation 17-1 shows the formula for computation of the baud rate with BRGH = 0. EQUATION 17-1: Baud Rate = The maximum baud rate (BRGH = 0) possible is FCY/16 (for UxBRG = 0) and the minimum baud rate possible is FCY/(16 * 65536). Equation 17-2 shows the formula for computation of the baud rate with BRGH = 1.
PIC24FJ64GA104 FAMILY 17.2 1. 2. 3. 4. 5. 6. Set up the UART: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the UxBRG register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UART. Set the UTXEN bit (causes a transmit interrupt two cycles after being set). Write data byte to the lower byte of the UxTXREG word.
PIC24FJ64GA104 FAMILY REGISTER 17-1: R/W-0 UxMODE: UARTx MODE REGISTER U-0 (1) UARTEN — R/W-0 USIDL R/W-0 IREN (2) R/W-0 U-0 R/W-0 R/W-0 RTSMD — UEN1 UEN0 bit 15 bit 8 R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bi
PIC24FJ64GA104 FAMILY REGISTER 17-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode (four BRG clock cycles per bit) 0 = Standard mode (16 BRG clock cycles per bit) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: 2: If UARTEN = 1, the peripheral inputs and out
PIC24FJ64GA104 FAMILY REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0 R-1 UTXISEL1 UTXINV(1) UTXISEL0 — UTXBRK UTXEN(2) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0 URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: C = Clearable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit i
PIC24FJ64GA104 FAMILY REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode is enabled. If 9-bit mode is not selected, this does not take effect.
PIC24FJ64GA104 FAMILY NOTES: DS39951C-page 190 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY 18.0 PARALLEL MASTER PORT (PMP) Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 13. “Parallel Master Port (PMP)” (DS39713).
PIC24FJ64GA104 FAMILY REGISTER 18-1: PMCON: PARALLEL PORT CONTROL REGISTER R/W-0 U-0 R/W-0 PMPEN — PSIDL R/W-0 R/W-0 ADRMUX1(1) ADRMUX0(1) R/W-0 R/W-0 R/W-0 PTBEEN PTWREN PTRDEN bit 15 bit 8 R/W-0 R/W-0 R/W-0(2) U-0 R/W-0(2) R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP — CS1P BEP WRSP RDSP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PMPEN: Parallel Ma
PIC24FJ64GA104 FAMILY REGISTER 18-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) bit 2 BEP: Byte Enable Polarity bit 1 = Byte enable active-high (PMBE) 0 = Byte enable active-low (PMBE) bit 1 WRSP: Write Strobe Polarity bit For Slave modes and Master Mode 2 (PMMODE<9:8> = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master Mode 1 (PMMODE<9:8> = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) bit 0 RDSP: Read Strobe Polarit
PIC24FJ64GA104 FAMILY REGISTER 18-2: PMMODE: PARALLEL PORT MODE REGISTER R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAITB1(1) WAITB0(1) WAITM3 WAITM2 WAITM1 WAITM0 WAITE1(1) WAITE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15
PIC24FJ64GA104 FAMILY REGISTER 18-3: PMADDR: PARALLEL PORT ADDRESS REGISTER U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — CS1 — — — ADDR10(1) ADDR9(1) ADDR8(1) bit 15 bit 8 R/W-0 ADDR7 (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR6(1) ADDR5(1) ADDR4(1) ADDR3(1) ADDR2(1) ADDR1(1) ADDR0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0
PIC24FJ64GA104 FAMILY REGISTER 18-5: PMSTAT: PARALLEL PORT STATUS REGISTER R-0 R/W-0, HS U-0 U-0 R-0 R-0 R-0 R-0 IBF IBOV — — IB3F IB2F IB1F IB0F bit 15 bit 8 R-1 R/W-0, HS U-0 U-0 R-1 R-1 R-1 R-1 OBE OBUF — — OB3E OB2E OB1E OB0E bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IBF: Input Buffer Full Status bit 1
PIC24FJ64GA104 FAMILY REGISTER 18-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 RTSECSEL1(1) RTSECSEL0(1) R/W-0 PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-1 RTSECSEL<1:0>: RTCC Seconds Clock O
PIC24FJ64GA104 FAMILY FIGURE 18-2: LEGACY PARALLEL SLAVE PORT EXAMPLE PIC24F Slave Master PMD<7:0> FIGURE 18-3: PMD<7:0> PMCS1 PMCS1 PMRD PMRD PMWR PMWR Address Bus Data Bus Control Lines ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE Master PIC24F Slave PMA<1:0> PMA<1:0> PMD<7:0> PMD<7:0> Write Address Decode Read Address Decode PMDOUT1L (0) PMDIN1L (0) PMCS1 PMCS1 PMDOUT1H (1) PMDIN1H (1) PMRD PMRD PMDOUT2L (2) PMDIN2L (2) PMWR PMWR PMDOUT2H (3) PMDIN2H (3) Address Bus Data Bus C
PIC24FJ64GA104 FAMILY FIGURE 18-5: MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, SINGLE CHIP SELECT) PIC24F PMA<10:8> PMD<7:0> PMA<7:0> PMCS1 Address Bus PMALL FIGURE 18-6: PMRD Multiplexed Data and Address Bus PMWR Control Lines MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, SINGLE CHIP SELECT) PMD<7:0> PMA<7:0> PMA<15:8> PIC24F PMCS1 PMALL PMALH FIGURE 18-7: PMRD Multiplexed Data and Address Bus PMWR Control Lines EXAMPLE OF
PIC24FJ64GA104 FAMILY FIGURE 18-9: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION PIC24F Parallel Peripheral PMD<7:0> PMALL AD<7:0> ALE PMCS1 CS Address Bus PMRD RD Data Bus PMWR WR Control Lines FIGURE 18-10: PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 8-BIT DATA) PIC24F PMA Parallel EEPROM A PMD<7:0> D<7:0> PMCS1 CE PMRD OE PMWR WR FIGURE 18-11: Address Bus Data Bus Control Lines PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 16-BIT DATA) Parallel EE
PIC24FJ64GA104 FAMILY 19.0 Note: REAL-TIME CLOCK AND CALENDAR (RTCC) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 29. “Real-Time Clock and Calendar (RTCC)” (DS39696). The RTCC provides the user with a Real-Time Clock and Calendar (RTCC) function that can be calibrated.
PIC24FJ64GA104 FAMILY 19.2 RTCC Module Registers TABLE 19-2: The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 19.2.1 To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTR bits (RCFGCAL<9:8>) to select the desired Timer register pair (see Table 19-1).
PIC24FJ64GA104 FAMILY 19.2.
PIC24FJ64GA104 FAMILY REGISTER 19-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED) bit 7-0 Note 1: 2: 3: CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute . . . 01111111 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute . . .
PIC24FJ64GA104 FAMILY REGISTER 19-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 ALRMEN bit 15 R/W-0 CHIME R/W-0 AMASK3 R/W-0 AMASK2 R/W-0 AMASK1 R/W-0 AMASK0 R/W-0 ALRMPTR1 R/W-0 ARPT7 bit 7 R/W-0 ARPT6 R/W-0 ARPT5 R/W-0 ARPT4 R/W-0 ARPT3 R/W-0 ARPT2 R/W-0 ARPT1 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13-10 bit 9-8 bit 7-0 W = Writable bit ‘1’ = Bit is set R/W-0 ALRMPTR0 bit 8 R/W-0 ARPT0 bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is u
PIC24FJ64GA104 FAMILY 19.2.
PIC24FJ64GA104 FAMILY REGISTER 19-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) U-0, HSC U-0, HSC U-0, HSC U-0, HSC U-0, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0, HSC U-0, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value a
PIC24FJ64GA104 FAMILY 19.2.
PIC24FJ64GA104 FAMILY REGISTER 19-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimple
PIC24FJ64GA104 FAMILY 19.3 Calibration The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than 3 seconds per month. This is accomplished by finding the number of error clock pulses and storing the value into the lower half of the RCFGCAL register. The 8-bit signed value loaded into the lower half of RCFGCAL is multiplied by four and will either be added or subtracted from the RTCC timer, once every minute.
PIC24FJ64GA104 FAMILY FIGURE 19-2: ALARM MASK SETTINGS Alarm Mask Setting (AMASK<3:0>) Day of the Week Month Day Hours Minutes Seconds 0000 - Every half second 0001 - Every second 0010 - Every 10 seconds s 0011 - Every minute s s m s s m m s s 0100 - Every 10 minutes 0101 - Every hour 0110 - Every day 0111 - Every week d 1000 - Every month 1001 - Every year(1) Note 1: m m h h m m s s h h m m s s d d h h m m s s d d h h m m s s Annually, except when confi
PIC24FJ64GA104 FAMILY NOTES: DS39951C-page 212 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY 20.0 Note: 32-BIT PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR The programmable CRC generator provides a hardware-implemented method of quickly generating checksums for various networking and security applications.
PIC24FJ64GA104 FAMILY 20.1 User Interface 20.1.1 POLYNOMIAL INTERFACE The CRC module can be programmed for CRC polynomials of up to the 32nd order, using up to 32 bits. Polynomial length, which reflects the highest exponent in the equation, is selected by the PLEN<4:0> bits (CRCCON2<4:0>). The CRCXORL and CRCXORH registers control which exponent terms are included in the equation.
PIC24FJ64GA104 FAMILY 20.1.3 DATA SHIFT DIRECTION The LENDIAN bit (CRCCON1<3>) is used to control the shift direction. By default, the CRC will shift data through the engine, MSb first. Setting LENDIAN (= 1) causes the CRC to shift data, LSb first. This setting allows better integration with various communication schemes and removes the overhead of reversing the bit order in software. Note that this only changes the direction of the data that is shifted into the engine.
PIC24FJ64GA104 FAMILY REGISTER 20-1: CRCCON1: CRC CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R-0 R-0 R-0 R-0 R-0 CRCEN — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 bit 15 bit 8 R-0, HCS R-1, HCS R/W-0 R/W-0, HC R/W-0 U-0 U-0 U-0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — bit 7 bit 0 Legend: HC = Hardware Clearable bit HCS = Hardware Clearable/Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cl
PIC24FJ64GA104 FAMILY REGISTER 20-2: CRCCON2: CRC CONTROL REGISTER 2 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 DWIDTH
PIC24FJ64GA104 FAMILY REGISTER 20-4: CRCXORH: CRC XOR POLYNOMIAL REGISTER, HIGH BYTE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X31 X30 X29 X28 X27 X26 X25 X24 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X23 X22 X21 X20 X19 X18 X17 X16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown X<31:16>: XOR of Polynomial Term Xn
PIC24FJ64GA104 FAMILY 21.0 Note: 10-BIT HIGH-SPEED A/D CONVERTER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 17. “10-Bit A/D Converter” (DS39705). A block diagram of the A/D Converter is shown in Figure 21-1. To perform an A/D conversion: 1.
PIC24FJ64GA104 FAMILY FIGURE 21-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVSS VREF+ VR Select AVDD VR+ 16 VR- VREF- Comparator VINH AN0 VINL VRS/H VR+ DAC AN1 AN2 AN5 MUX A AN4 10-Bit SAR VINH AN3 Conversion Logic Data Formatting AN6 ADC1BUF0: ADC1BUFF VINL AN7 AN8 AD1CON1 AN9 AD1CON2 AD1CON3 AD1CHS0 AN10 AN12 VDDCORE VBG/2 MUX B AN11 VINH AD1PCFGL AD1PCFGH AD1CSSL AD1CSSH VINL VBG Sample Control Control Logic Conversion Control Input MUX Cont
PIC24FJ64GA104 FAMILY REGISTER 21-1: AD1CON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 ADON(1) — ADSIDL — — — FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0, HCS R/C-0, HCS SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE bit 7 bit 0 Legend: C = Clearable bit HCS = Hardware Clearable/Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unkno
PIC24FJ64GA104 FAMILY REGISTER 21-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 r-0 U-0 R/W-0 U-0 U-0 VCFG2 VCFG1 VCFG0 r — CSCNA — — bit 15 bit 8 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 x = Bit is unknown VCFG<2:0>: Voltage Reference Confi
PIC24FJ64GA104 FAMILY REGISTER 21-3: AD1CON3: A/D CONTROL REGISTER 3 R/W-0 r-0 r-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC r r SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADRC: A/D Conversion Clock Source b
PIC24FJ64GA104 FAMILY REGISTER 21-4: AD1CHS: A/D INPUT SELECT REGISTER R/W-0 U-0 U-0 CH0NB — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0SB4(1,2) CH0SB3(1,2) CH0SB2(1,2) CH0SB1(1,2) CH0SB0(1,2) bit 15 bit 8 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA — — CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CH0NB: Chann
PIC24FJ64GA104 FAMILY REGISTER 21-5: AD1PCFG: A/D PORT CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0(1) R/W-0 R/W-0 R/W-0 R/W-0(1) PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 bit 15 bit 8 R/W-0(1) R/W-0(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bi
PIC24FJ64GA104 FAMILY REGISTER 21-6: AD1CSSL: A/D INPUT SCAN SELECT REGISTER R/W-0 R/W-0 R/W-0 R/W-0(1) R/W-0 R/W-0 R/W-0 R/W-0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 C
PIC24FJ64GA104 FAMILY A/D CONVERSION CLOCK PERIOD(1) EQUATION 21-1: ADCS = TAD –1 TCY TAD = TCY • (ADCS + 1) Note 1: FIGURE 21-2: Based on TCY = 2 * TOSC, Doze mode and PLL are disabled. 10-BIT A/D CONVERTER ANALOG INPUT MODEL VDD Rs VA RIC 250 VT = 0.6V ANx CPIN 6-11 pF (Typical) VT = 0.6V Sampling Switch RSS 5 k(Typical) RSS ILEAKAGE 500 nA CHOLD = ADC capacitance = 4.
PIC24FJ64GA104 FAMILY FIGURE 21-3: A/D TRANSFER FUNCTION Output Code (Binary (Decimal)) 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1) DS39951C-page 228 (VINH – VINL) VR+ 1024 1023*(VR+ – VR-) VR- + 1024 VR- + 512*(VR+ – VR-) 1024 VR- + Voltage Level VR+ – VR- 0 VR- 00 0000 0000 (0) 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY 22.0 TRIPLE COMPARATOR MODULE Note: The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals ‘1’, the I/O pad logic makes the unsynchronized output of the comparator available on the pin. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated “PIC24F Family Reference Manual”, Section 46.
PIC24FJ64GA104 FAMILY FIGURE 22-2: INDIVIDUAL COMPARATOR CONFIGURATIONS Comparator Off CEN = 0, CREF = x, CCH<1:0> = xx COE VINVIN+ Cx Off (Read as ‘0’) Comparator CxINB > CxINA Compare CEN = 1, CREF = 0, CCH<1:0> = 00 CXINB CXINA VIN+ Comparator CxINC > CxINA Compare CEN = 1, CREF = 0, CCH<1:0> = 01 COE VIN- CXINC Cx CxOUT Pin CXINA COE VINVIN+ CVREF- Cx CxOUT Pin Comparator CxINB > CVREF+ Compare CEN = 1, CREF = 1, CCH<1:0> = 00 CXINB CVREF+ CXINC Cx CxOUT Pin CVREF+ DS39951C-page 2
PIC24FJ64GA104 FAMILY REGISTER 22-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R-0 CEN COE CPOL — — — CEVT COUT bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CEN: Comparator Enable bit 1 = Com
PIC24FJ64GA104 FAMILY REGISTER 22-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) (CONTINUED) bit 4 CREF: Comparator Reference Select bits (non-inverting input) 1 = Non-inverting input connects to internal CVREF+ input reference voltage 0 = Non-inverting input connects to CxINA pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of comparator connects to CVREF- input reference voltage 10 = Inverting input of comparator conne
PIC24FJ64GA104 FAMILY 23.0 COMPARATOR VOLTAGE REFERENCE Note: 23.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 20. “Comparator Voltage Reference Module” (DS39709). Configuring the Comparator Voltage Reference voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>).
PIC24FJ64GA104 FAMILY REGISTER 23-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CVREFP CVREFM1 CVREFM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’
PIC24FJ64GA104 FAMILY 24.0 Note: CHARGE TIME MEASUREMENT UNIT (CTMU) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated “PIC24F Family Reference Manual”, Section 11. “Charge Time Measurement Unit (CTMU)” (DS39724).
PIC24FJ64GA104 FAMILY 24.2 Measuring Time When the module is configured for pulse generation delay by setting the TGEN bit (CTMUCON<12>), the internal current source is connected to the B input of Comparator 2. A capacitor (CDELAY) is connected to the Comparator 2 pin, C2INB, and the comparator voltage reference, CVREF, is connected to C2INA. CVREF is then configured for a specific trip point. The module begins to charge CDELAY when an edge event is detected.
PIC24FJ64GA104 FAMILY REGISTER 24-1: R/W-0 CTMUCON: CTMU CONTROL REGISTER U-0 CTMUEN R/W-0 — CTMUSIDL R/W-0 (1) TGEN R/W-0 R/W-0 R/W-0 R/W-0 EDGEN EDGSEQEN IDISSEN CTTRIG bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CTMUEN: CTMU En
PIC24FJ64GA104 FAMILY REGISTER 24-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 3-2 EDG1SEL<1:0>: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module bit 1 EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred bit 0 EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred Note 1: If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin.
PIC24FJ64GA104 FAMILY 25.0 Note: SPECIAL FEATURES 25.1.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the following sections of the “PIC24F Family Reference Manual”: In PIC24FJ64GA104 family devices, the configuration bytes are implemented as volatile memory. This means that configuration data must be programmed each time the device is powered up.
PIC24FJ64GA104 FAMILY REGISTER 25-1: CW1: FLASH CONFIGURATION WORD 1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 r-x R/PO-1 R/PO-1 R/PO-1 R/PO-1 U-1 R/PO-1 R/PO-1 r JTAGEN(1) GCP GWRP DEBUG — ICS1 ICS0 bit 15 bit 8 R/PO-1 R/PO-1 U-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 FWDTEN WINDIS — FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit PO = Program Once bit -n = Value when device is unprogrammed
PIC24FJ64GA104 FAMILY REGISTER 25-1: bit 3-0 Note 1: CW1: FLASH CONFIGURATION WORD 1 (CONTINUED) WDTPS<3:0>: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 The JTAGEN bit can only be modified using In-Circuit Serial Programming™ (ICSP™). It cannot be modified while connected through the JTAG interface.
PIC24FJ64GA104 FAMILY REGISTER 25-2: CW2: FLASH CONFIGURATION WORD 2 U-1 — bit 23 U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — R/PO-1 IESO bit 15 U-1 — U-1 — U-1 — U-1 — R/PO-1 FNOSC2 R/PO-1 FNOSC1 R/PO-1 FNOSC0 bit 8 R/PO-1 FCKSM1 bit 7 R/PO-1 FCKSM0 R/PO-1 OSCIOFCN R/PO-1 IOL1WAY U-1 — R/PO-1 I2C1SEL R/PO-1 POSCMD1 R/PO-1 POSCMD0 bit 0 Legend: R = Readable bit PO = Program Once bit -n = Value when device is unprogrammed bit 23-16 bit 15 bit 14-11 bit 10-8 bit 7-6 bit 5 bit 4 bit 3 bit
PIC24FJ64GA104 FAMILY REGISTER 25-3: U-1 — bit 23 R/PO-1 WPEND bit 15 U-1 — CW3: FLASH CONFIGURATION WORD 3 U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — bit 16 R/PO-1 WPCFG R/PO-1 WPDIS U-1 — R/PO-1 WUTSEL1 R/PO-1 WUTSEL0 R/PO-1 SOSCSEL1(1) U-1 — R/PO-1 WPFP5 R/PO-1 WPFP4 R/PO-1 WPFP3 R/PO-1 WPFP2 R/PO-1 WPFP1 R/PO-1 SOSCSEL0(1) bit 8 R/PO-1 WPFP0 bit 0 bit 7 Legend: R = Readable bit PO = Program Once bit -n = Value when device is unprogrammed bit 23-16 bit 15 bit 14 bit 13 bit 12 bit 1
PIC24FJ64GA104 FAMILY REGISTER 25-4: CW4: FLASH CONFIGURATION WORD 4 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 DSWDTEN DSBOREN RTCOSC R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 DSWDTOSC DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 bit 7 bit 0 Legend: R = Readable bit PO = Program Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ ‘1’ = Bi
PIC24FJ64GA104 FAMILY REGISTER 25-5: U — bit 23 DEVID: DEVICE ID REGISTER U — U — U — U — U — U — R FAMID7 bit 15 R FAMID6 R FAMID5 R FAMID4 R FAMID3 R FAMID2 R FAMID1 R FAMID0 bit 8 R DEV7 bit 7 R DEV6 R DEV5 R DEV4 R DEV3 R DEV2 R DEV1 R DEV0 bit 0 Legend: R = Read-Only bit bit 23-16 bit 15-8 bit 7-0 U — bit 16 U = Unimplemented bit Unimplemented: Read as ‘1’ FAMID<7:0>: Device Family Identifier bits 01000010 = PIC24FJ64GA104 family DEV<7:0>: Individual Device Identifier bits 000
PIC24FJ64GA104 FAMILY 25.2 On-Chip Voltage Regulator All PIC24FJ64GA104 family devices power their core digital logic at a nominal 2.5V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ64GA104 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the DISVREG pin.
PIC24FJ64GA104 FAMILY When waking up from Sleep with the regulator disabled, TPM is used to determine the wake-up time. To decrease the device wake-up time when operating with the regulator disabled, the PMSLP bit can be set. 25.3 25.2.3 The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit.
PIC24FJ64GA104 FAMILY 25.3.1 WINDOWED OPERATION 25.3.2 The Watchdog Timer has an optional Fixed Window mode of operation. In this Windowed mode, CLRWDT instructions can only reset the WDT during the last 1/4 of the programmed WDT period. A CLRWDT instruction is executed before that window causes a WDT Reset; this is similar to a WDT time-out. Windowed WDT mode is enabled by programming the WINDIS Configuration bit (CW1<6>) to ‘0’.
PIC24FJ64GA104 FAMILY 25.5.2 CODE SEGMENT PROTECTION In addition to global General Segment protection, a separate subrange of the program memory space can be individually protected against writes and erases. This area can be used for many purposes where a separate block of erase and write-protected code is needed, such as bootloader applications.
PIC24FJ64GA104 FAMILY 25.6 JTAG Interface PIC24FJ64GA104 family devices implement a JTAG interface, which supports boundary scan device testing. 25.7 In-Circuit Serial Programming PIC24FJ64GA104 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock (PGECx) and data (PGEDx), and three other lines for power, ground and the programming voltage.
PIC24FJ64GA104 FAMILY 26.
PIC24FJ64GA104 FAMILY 26.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
PIC24FJ64GA104 FAMILY 26.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC24FJ64GA104 FAMILY 26.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 26.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC24FJ64GA104 FAMILY 27.0 Note: INSTRUCTION SET SUMMARY This chapter is a brief summary of the PIC24F instruction set architecture, and is not intended to be a comprehensive reference source. The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations.
PIC24FJ64GA104 FAMILY TABLE 27-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) {0...
PIC24FJ64GA104 FAMILY TABLE 27-2: INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW BTG BTSC Assembly Syntax Description # of Words # of Cycles Status Flags Affected ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC f f = f + WREG + (C) 1 1 C,
PIC24FJ64GA104 FAMILY TABLE 27-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSS BTST BTSTS Assembly Syntax Description # of Words # of Cycles Status Flags Affected BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws to C 1 1 C Z BTST.
PIC24FJ64GA104 FAMILY TABLE 27-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic GOTO INC INC2 Assembly Syntax Description # of Words # of Cycles Status Flags Affected GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC f f=f+1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 INC2 f f=f+2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC2 Ws
PIC24FJ64GA104 FAMILY TABLE 27-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None RESET RESET Software Device Reset 1 1 Non
PIC24FJ64GA104 FAMILY TABLE 27-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR.
PIC24FJ64GA104 FAMILY NOTES: DS39951C-page 262 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY 28.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FJ64GA104 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ64GA104 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
PIC24FJ64GA104 FAMILY 28.1 DC Characteristics FIGURE 28-1: PIC24FJ64GA104 FAMILY VOLTAGE/FREQUENCY GRAPH (INDUSTRIAL) 3.00V Voltage (VDDCORE)(1) 2.75V 2.75V 2.50V PIC24FJ64GA104 Family 2.35V 2.35V 2.00V 16 MHz Frequency 32 MHz For frequencies between 16 MHz and 32 MHz, FMAX = (45.7 MHz/V) * (VDDCORE – 2V) + 16 MHz. When the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCOREVDD3.6V.
PIC24FJ64GA104 FAMILY TABLE 28-1: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Operating Junction Temperature Range TJ -40 — +140 °C Operating Ambient Temperature Range TA -40 — +125 °C PIC24FJ64GA104 Family: Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD – IOH) PD PINT + PI/O W PDMAX (TJ – TA)/JA W I/O Pin Power Dissipation: PI/O = ({VDD – VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation TABLE 28-2: THERMAL PACKAGING CHARA
PIC24FJ64GA104 FAMILY TABLE 28-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min Typ(1) Max Units VDD 2.2 — 3.6 V Regulator enabled VDD VDDCORE — 3.6 V Regulator disabled 2.0 — 2.
PIC24FJ64GA104 FAMILY TABLE 28-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Operating Current (IDD)(2) DC21 0.24 0.395 mA -40°C DC21a 0.25 0.395 mA +25°C DC21b 0.25 0.395 mA +85°C DC21f 0.3 0.395 mA +125°C DC21c 0.44 0.78 mA -40°C DC21d 0.41 0.
PIC24FJ64GA104 FAMILY TABLE 28-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Operating Current (IDD)(2) DC24 10.5 15.5 mA -40°C DC24a 10.5 15.5 mA +25°C DC24b 10.5 15.5 mA +85°C DC24c 11.3 15.5 mA +125°C DC24d 11.3 15.5 mA -40°C DC24e 11.
PIC24FJ64GA104 FAMILY TABLE 28-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Parameter No.
PIC24FJ64GA104 FAMILY TABLE 28-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) -40°C TA +125°C for Extended Max Units Conditions Idle Current (IIDLE)(2) DC50 0.8 1.0 mA -40°C DC50a 0.8 1.0 mA +25°C DC50b 0.8 1.0 mA +85°C DC50c 0.9 1.1 mA +125°C DC50d 1.1 1.3 mA -40°C DC50e 1.1 1.
PIC24FJ64GA104 FAMILY TABLE 28-6: DC CHARACTERISTICS: POWER-DOWN BASE CURRENT (IPD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units 1.0 A Conditions Power-Down Current (IPD)(2) DC60 0.05 -40°C DC60a 0.2 1.0 A +25°C DC60i 2.0 6.5 A +60°C DC60b 3.5 12 A +85°C DC60m 29.9 50 A +125°C DC60c 0.1 1.
PIC24FJ64GA104 FAMILY TABLE 28-7: DC CHARACTERISTICS: POWER-DOWN PERIPHERAL MODULE CURRENT (IPD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) DC61 0.2 0.7 A -40°C DC61a 0.2 0.7 A +25°C DC61i 0.2 0.7 A +60°C DC61b 0.23 0.
PIC24FJ64GA104 FAMILY TABLE 28-7: DC CHARACTERISTICS: POWER-DOWN PERIPHERAL MODULE CURRENT (IPD) (CONTINUED) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) DC63 1.8 2.3 A -40°C DC63a 1.8 2.7 A +25°C DC63i 1.8 3.0 A +60°C DC63b 1.8 3.
PIC24FJ64GA104 FAMILY TABLE 28-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param No. Sym VIL Characteristic Min Typ(1) Max Units Input Low Voltage(4) DI10 I/O Pins with ST Buffer VSS — 0.2 VDD V DI11 I/O Pins with TTL Buffer VSS — 0.15 VDD V DI15 MCLR VSS — 0.
PIC24FJ64GA104 FAMILY TABLE 28-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param No. Sym VOL Characteristic I/O Ports DO16 I/O Ports VOH Note 1: Max Units — — 0.4 V IOL = 8.5 mA, VDD = 3.6V — — 0.4 V IOL = 5.0 mA, VDD = 2.0V — — 0.4 V IOL = 8.0 mA, VDD = 3.6V, 125°C — — 0.4 V IOL = 4.
PIC24FJ64GA104 FAMILY TABLE 28-11: COMPARATOR SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param No.
PIC24FJ64GA104 FAMILY 28.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FJ64GA104 family AC characteristics and timing parameters. TABLE 28-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial and -40°C TA +125°C for Extended Operating voltage VDD range as described in Section 28.1 “DC Characteristics”.
PIC24FJ64GA104 FAMILY FIGURE 28-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS40 OS41 TABLE 28-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.50 to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Sym No.
PIC24FJ64GA104 FAMILY TABLE 28-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
PIC24FJ64GA104 FAMILY FIGURE 28-5: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 28-3 for load conditions. TABLE 28-20: CLKO AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
PIC24FJ64GA104 FAMILY TABLE 28-22: ADC MODULE SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply Greater of VDD – 0.3 or 2.0 — Lesser of VDD + 0.3 or 3.6 V AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.
PIC24FJ64GA104 FAMILY TABLE 28-23: ADC CONVERSION TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max.
PIC24FJ64GA104 FAMILY 29.0 PACKAGING INFORMATION 29.1 Package Marking Information Example 28-Lead QFN 24FJ32GA 102/ML e3 1010017 XXXXXXXX XXXXXXXX YYWWNNN Example 28-Lead SOIC (.300”) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN Example 28-Lead SPDIP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP PIC24FJ32GA102 -I/SP e3 1010017 Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PIC24FJ64GA104 FAMILY 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS39951C-page 284 Example 24FJ32GA 104-I/ML e3 1010017 Example 24FJ32GA 104-I/PT e3 1010017 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY 29.2 Package Details The following sections give the technical details of the packages. ! " # $ %&'' ( ) ) $ * 2 % & % ! % * %% 133))) & &3 " ) * D ' % * $ % % " % D2 EXPOSED PAD e E b E2 2 2 1 1 N K N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 4 % & 5 & % 6!&( $ 55 , , 6 6 67 8 9 % :.
PIC24FJ64GA104 FAMILY ! " # $ %&'' ( ) ) $ * 2 % & % ! % * %% 133))) & &3 DS39951C-page 286 " ) * ' % * $ % % " % 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY * + , ) +, - .&'% !+,/(" 2 % & % ! % * %% 133))) & &3 " ) * ' % * $ % % " % D N E E1 NOTE 1 1 2 3 e b h α A2 A h c φ L A1 β L1 4 % & 5 & % 6!&( $ 55 , , 6 6 / 0 7 ; % * % " $$ ? 7 < "% " " * 8 9 % " " * 67 > > . > > > + , < "% 7 5 % :.
PIC24FJ64GA104 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39951C-page 288 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY + )) * 0 /) ) + 1%% !+ 0/ " 2 % & % ! % * %% 133))) & &3 " ) * ' % * $ % % " % N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 4 % & 5 & % 6!&( $ 60;, 6 6 67 8 9 % / 0 % % > > +. . . > > ! " % ! " < "% , + ++.
PIC24FJ64GA104 FAMILY 22 * ! " 2 % & % ! % * %% 133))) & &3 " ) * ' D % * $ % % " % D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 K L TOP VIEW BOTTOM VIEW A A3 A1 4 % & 5 & % 6!&( $ 55 , , 6 67 6 8 % :. / 0 7 ; % 9 % " $$ .
PIC24FJ64GA104 FAMILY 22 * ! " 2 % & % ! % * %% 133))) & &3 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY 22 * 3$ ) 4 3 5% 5% 5 &%% !3 " 2 % & % ! % * %% 133))) & &3 " ) * ' % * $ % % " % D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A φ c β A2 A1 L L1 4 % & 5 & % 6!&( $ 5 5 " 55 , , 6 67 6 8 " % 9 / 0 7 ; % > > . . . > . 2 % 5 % 5 . : .
PIC24FJ64GA104 FAMILY 22 * 3$ ) 4 3 5% 5% 5 &%% !3 " 2 % & % ! % * %% 133))) & &3 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY * +$6 ) + , ) ++ '&1% !++, " 2 % & % ! % * %% 133))) & &3 " ) * ' % * $ % % " % D N E E1 1 2 NOTE 1 b e c A2 A φ A1 L L1 4 % & 5 & % 6!&( $ 55 , , 6 6 67 8 9 % :. / 0 7 ; % > > :. . 9. % " $$ . > > 7 < "% , 9 9 " " * " " * * , .
PIC24FJ64GA104 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY NOTES: DS39951C-page 296 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY APPENDIX A: REVISION HISTORY Revision A (August 2009) Original data sheet for the PIC24FJ64GA104 family of devices. Revision B (October 2009) Corrected Section 10.3 “Input Change Notification” regarding the number of ICN inputs and the availability of pull-downs. Updated Section 10.4.2 “Available Peripherals” by removing the Timer 1 clock input from Table 10-2. Updated Section 28.
PIC24FJ64GA104 FAMILY NOTES: DS39951C-page 298 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY INDEX A Partially Multiplexed Addressing Application Example ........................................................... 199 PIC24F CPU Core ...................................................... 26 PIC24FJ64GA104 Family (General)........................... 12 PMP Module Overview ............................................. 191 PSV Operation............................................................ 50 Reset System .............................................................
PIC24FJ64GA104 FAMILY CRC Registers ................................................................... 215 Typical Operation ...................................................... 215 User Interface ........................................................... 214 Data .................................................................. 214 Polynomial ........................................................ 214 CTMU Measuring Capacitance ............................................ 235 Measuring Time .........
PIC24FJ64GA104 FAMILY N Near Data Space ................................................................ 34 O Oscillator Configuration Bit Values for Clock Selection................................... 102 Clock Switching......................................................... 106 Sequence.......................................................... 107 Control Registers ...................................................... 103 CPU Clocking Scheme .............................................
PIC24FJ64GA104 FAMILY IPC1 (Interrupt Priority Control 1) ............................... 83 IPC10 (Interrupt Priority Control 10) ........................... 92 IPC11 (Interrupt Priority Control 11) ........................... 93 IPC12 (Interrupt Priority Control 12) ........................... 94 IPC15 (Interrupt Priority Control 15) ........................... 95 IPC16 (Interrupt Priority Control 16) ........................... 96 IPC18 (Interrupt Priority Control 18) ...........................
PIC24FJ64GA104 FAMILY V W VDDCORE/VCAP Pin............................................................ 246 Voltage Regulator (On-Chip) ............................................ 246 and BOR ................................................................... 247 and POR ................................................................... 246 Power-up Requirements ........................................... 247 Standby Mode........................................................... 247 Tracking Mode ......
PIC24FJ64GA104 FAMILY NOTES: DS39951C-page 304 2010 Microchip Technology Inc.
PIC24FJ64GA104 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC24FJ64GA104 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC24FJ64GA104 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FJ 64 GA1 04 T - I / PT - XXX Examples: a) Microchip Trademark Architecture Flash Memory Family b) Program Memory Size (KB) PIC24FJ64GA104-I/PT: PIC24F device with, 64-Kbyte program memory, 44-pin, Industrial temp., TQFP package. PIC24FJ32GA102-I/ML: PIC24F device with32-Kbyte program memory, 28-pin, Industrial temp.,QFN package.
WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.