Datasheet

 2010 Microchip Technology Inc. DS39951C-page 297
PIC24FJ64GA104 FAMILY
APPENDIX A: REVISION HISTORY
Revision A (August 2009)
Original data sheet for the PIC24FJ64GA104 family of
devices.
Revision B (October 2009)
Corrected Section 10.3 “Input Change Notification”
regarding the number of ICN inputs and the availability
of pull-downs.
Updated Section 10.4.2 “Available Peripherals” by
removing the Timer 1 clock input from Table 10-2.
Updated Section 28.1 “DC Characteristics” as
follows:
• Added new specifications to Tables 29-4 and 29-5
for I
DD and IIDLE at 0.5 MIPS operation.
• Updated Table 29-4 with revised maximum IDD
specifications for 1 MIP and 4 MIPS.
• Renumbered the parameters for the delta I
PD
current (32 kHz, SOSCEL = 11) from DC62n to
DC63n.
Revision C (August 2010)
This revision includes the following updates:
Pin Diagrams
• Updated Pin 7 and Pin 14 in 28-Pin SPDIP, SOIC.
• Updated the device name, Pin13 and Pin 23, in
28-Pin QFN.
Removed IEC5, IFS5 and IPC21 rows from Table 4-5.
Updated CLKDIV bit details in Table 4-23.
Removed JTAG from Flash programming list in
Section 5.0 “Flash Program Memory”.
Updated Section 10.4.5 “Considerations for
Peripheral Pin Selection” as follows:
• Replaced the code in Example 10-2.
• Added the new code as Example 10-3.
Updated shaded note in Section 20.0 “32-Bit Pro-
grammable Cyclic Redundancy Check (CRC)
Generator” and Section 22.0 “Triple Comparator
Module”.
Updated Section 28.1 “DC Characteristics” as
follows:
• Updated the device name in Table 28-1.
• Added the “125°C data” in
Table 28-4,Table 28-5,Table 28-6 and Table 28-7.
• Updated Min and Typ columns of DC16 in
Table 28-3.
• Added rows, AD08 and AD09, in Table 28-22.
• Added Figure 28-2.
Added the 28-pin SSOP package to Section 29.0
“Packaging Information”.