Datasheet

 2010 Microchip Technology Inc. DS39951C-page 225
PIC24FJ64GA104 FAMILY
REGISTER 21-5: AD1PCFG: A/D PORT CONFIGURATION REGISTER
R/W-0 R/W-0 R/W-0 R/W-0
(1)
R/W-0 R/W-0 R/W-0 R/W-0
(1)
PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8
bit 15 bit 8
R/W
-0
(1)
R/W-0
(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PCFG15: A/D Input Band Gap Reference Enable bit
1 = Internal band gap (V
BG) reference channel is disabled
0 = Internal band gap reference channel is enabled
bit 14 PCFG14: A/D Input Half Band Gap Reference Enable bit
1 = Internal half band gap (V
BG/2) reference channel is disabled
0 = Internal half band gap reference channel is enabled
bit 13 PCFG13: A/D Input Voltage Regulator Output Reference Enable bit
1 = Internal voltage regulator output (V
DDCORE) reference channel is disabled
0 = Internal voltage regulator output reference channel is enabled
bit 12-0 PCFG<12:0>: Analog Input Pin Configuration Control bits
(1)
1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read is enabled
0 = Pin is configured in Analog mode; I/O port read is disabled, A/D samples pin voltage
Note 1: Analog channels, AN6, AN7, AN8 and AN12, are unavailable on 28-pin devices; leave these corresponding
bits set.