Datasheet

 2010 Microchip Technology Inc. DS39951C-page 147
PIC24FJ64GA104 FAMILY
FIGURE 12-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
FIGURE 12-3: TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM
TON
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TCY
TCS
(1)
1x
01
TGATE
(1)
00
Gate
T2CK
Sync
PR2 (PR4)
Set T2IF (T4IF)
Equal
Comparator
TMR2 (TMR4)
Reset
Q
QD
CK
TGATE
1
0
(T4CK)
Sync
Note 1: The timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral
Pin Select (PPS)” for more information.
TON
TCKPS<1:0>
2
T
CY
TCS
(1)
1x
01
TGATE
(1)
00
T3CK
PR3 (PR5)
Set T3IF (T5IF)
Equal
Comparator
TMR3 (TMR5)
Reset
Q
QD
CK
TGATE
1
0
ADC Event Trigger
(2)
(T5CK)
Prescaler
1, 8, 64, 256
Sync
Note 1: The timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral
Pin Select (PPS)” for more information.
2: The ADC event trigger is available only on Timer3.