Datasheet

PIC24FJ64GA104 FAMILY
DS39951C-page 116  2010 Microchip Technology Inc.
9.2.4.10 Power-on Resets (PORs)
VDD voltage is monitored to produce PORs. Since exit-
ing from Deep Sleep functionally looks like a POR, the
technique described in Section 9.2.4.9 “Checking
and Clearing the Status of Deep Sleep” should be
used to distinguish between Deep Sleep and a true
POR event.
When a true POR occurs, the entire device, including
all Deep Sleep logic (Deep Sleep registers, RTCC,
DSWDT, etc.) is reset.
9.2.4.11 Summary of Deep Sleep Sequence
To review, these are the necessary steps involved in
invoking and exiting Deep Sleep mode:
1. Device exits Reset and begins to execute its
application code.
2. If DSWDT functionality is required, program the
appropriate Configuration bit.
3. Select the appropriate clock(s) for the DSWDT
and RTCC (optional).
4. Enable and configure the RTCC (optional).
5. Write context data to the DSGPRx registers
(optional).
6. Enable the INT0 interrupt (optional).
7. Set the DSEN bit in the DSCON register.
8. Enter Deep Sleep by issuing a PWRSV
#SLEEP_MODE command.
9. Device exits Deep Sleep when a wake-up event
occurs.
10. The DSEN bit is automatically cleared.
11. Read and clear the DPSLP status bit in RCON,
and the DSWAKE status bits.
12. Read the DSGPRx registers (optional).
13. Once all state related configurations are
complete, clear the RELEASE bit.
14. Application resumes normal operation.