Datasheet

PIC24FJ64GA004 FAMILY
DS39881E-page 168  2010-2013 Microchip Technology Inc.
REGISTER 18-1: PMCON: PARALLEL PORT CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMPEN
— PSIDL ADRMUX1
(1)
ADRMUX0
(1)
PTBEEN PTWREN PTRDEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0
(2)
U-0 R/W-0
(2)
R/W-0 R/W-0 R/W-0
CSF1 CSF0 ALP — CS1P BEP WRSP RDSP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PMPEN: PMP Enable bit
1 = PMP is enabled
0 = PMP is disabled, no off-chip access is performed
bit 14 Unimplemented: Read as ‘0’
bit 13 PSIDL: PMP Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits
(1)
11 = Reserved
10 = All 16 bits of address are multiplexed on the PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on the PMD<7:0> pins, upper 3 bits are multiplexed on
PMA<10:8>
00 = Address and data appear on separate pins
bit 10 PTBEEN: PMP Byte Enable Port Enable bit (16-Bit Master mode)
1 = PMBE port is enabled
0 = PMBE port is disabled
bit 9 PTWREN: PMP Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port is enabled
0 = PMWR/PMENB port is disabled
bit 8 PTRDEN: PMP Read/Write Strobe Port Enable bit
1 = PMRD/PMWR
port is enabled
0 = PMRD/PMWR
port is disabled
bit 7-6 CSF<1:0>: Chip Select Function bits
11 = Reserved
10 = PMCS1 functions as chip set
01 = Reserved
00 = Reserved
bit 5 ALP: Address Latch Polarity bit
(2)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL
and PMALH)
bit 4 Unimplemented: Read as ‘0’
bit 3 CS1P: Chip Select 1 Polarity bit
(2)
1 = Active-high (PMCS1/PMCS1)
0 =Active-low (PMCS1
/PMCS1)
Note 1: PMA<10:2> bits are not available on 28-pin devices.
2: These bits have no effect when their corresponding pins are used as address lines.