Datasheet

 2010-2013 Microchip Technology Inc. DS39881E-page 141
PIC24FJ64GA004 FAMILY
15.0 SERIAL PERIPHERAL
INTERFACE (SPI)
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface useful for communicating
with other peripheral or microcontroller devices. These
peripheral devices may be serial EEPROMs, shift reg-
isters, display drivers, A/D Converters, etc. The SPI
module is compatible with the SPI and SIOP Motorola
®
interfaces.
The module supports operation in two buffer modes. In
Standard mode, data is shifted through a single serial
buffer. In Enhanced Buffer mode, data is shifted
through an 8-level FIFO buffer.
The module also supports a basic framed SPI protocol
while operating in either Master or Slave mode. A total
of four framed SPI configurations are supported.
The SPI serial interface consists of four pins:
• SDIx: Serial Data Input
• SDOx: Serial Data Output
• SCKx: Shift Clock Input or Output
• SSx
: Active-Low Slave Select or Frame
Synchronization I/O Pulse
The SPI module can be configured to operate using 2,
3 or 4 pins. In the 3-pin mode, SSx
is not used. In the
2-pin mode, both SDOx and SSx
are not used.
Block diagrams of the module in Standard and
Enhanced modes are shown in Figure 15-1 and
Figure 15-2.
Depending on the pin count, PIC24FJ64GA004 family
devices offer one or two SPI modules on a single
device.
To set up the SPIx module for the Standard Master
mode of operation:
1. If using interrupts:
a) Clear the SPIxIF bit in the respective IFSx
register.
b) Set the SPIxIE bit in the respective IECx
register.
c) Write the SPIxIP bits in the respective IPCx
register to set the interrupt priority.
2. Write the desired settings to the SPIxCON1
and SPIxCON2 registers with the MSTEN bit
(SPIxCON1<5>) = 1.
3. Clear the SPIROV bit (SPIxSTAT<6>).
4. Enable SPIx operation by setting the SPIEN bit
(SPIxSTAT<15>).
5. Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start
as soon as data is written to the SPIxBUF
register.
To set up the SPIx module for the Standard Slave mode
of operation:
1. Clear the SPIxBUF register.
2. If using interrupts:
a) Clear the SPIxIF bit in the respective IFSx
register.
b) Set the SPIxIE bit in the respective IECx
register.
c) Write the SPIxIP bits in the respective IPCx
register to set the interrupt priority.
3. Write the desired settings to the SPIxCON1
and SPIxCON2 registers with the MSTEN bit
(SPIxCON1<5>) = 0.
4. Clear the SMP bit (SPIxCON1<9>).
5. If the CKE bit is set, then the SSEN bit
(SPIxCON1<7>) must be set to enable the SSx
pin.
6. Clear the SPIROV bit (SPIxSTAT<6>).
7. Enable SPIx operation by setting the SPIEN bit
(SPIxSTAT<15>).
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
“Serial Peripheral Interface (SPI)”
(DS39699)
Note: Do not perform read-modify-write opera-
tions (such as bit-oriented instructions) on
the SPIxBUF register in either Standard or
Enhanced Buffer mode.
Note: In this section, the SPI modules are
referred to together as SPIx or separately
as SPI1 and SPI2. Special Function Reg-
isters will follow a similar notation. For
example, SPIxCON1 or SPIxCON2 refers
to the control register for the SPI1 or SPI2
module.