Datasheet

PIC24FJ64GA004 FAMILY
DS39881E-page 106  2010-2013 Microchip Technology Inc.
10.1.1 OPEN-DRAIN CONFIGURATION
In addition to the PORT, LAT and TRIS registers for
data control, each port pin can also be individually con-
figured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits con-
figures the corresponding pin to act as an open-drain
output.
The open-drain feature allows the generation of
outputs higher than V
DD (e.g., 5V) on any desired
digital only pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum V
IH specification.
10.2 Configuring Analog Port Pins
The use of the AD1PCFG and TRIS registers control
the operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (V
OH or VOL) will be
converted.
When reading the PORT register, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) may cause the
input buffer to consume current that exceeds the
device specifications.
10.2.1 I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP.
10.2.2 ANALOG INPUT PINS AND
VOLTAGE CONSIDERATIONS
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Pins that are used
as digital only inputs are able to handle DC voltages up
to 5.5V, a level typical for digital logic circuits. In contrast,
pins that also have analog input functions of any kind
can only tolerate voltages up to V
DD. Voltage excursions
beyond V
DD on these pins are always to be avoided.
Table 10-1 summarizes the input capabilities. Refer to
Section 27.1 “DC Characteristics” for more details.
TABLE 10-1: INPUT VOLTAGE LEVELS
10.3 Input Change Notification
The Input Change Notification function of the I/O ports
allows the PIC24FJ64GA004 family of devices to gen-
erate interrupt requests to the processor in response to
a Change-of-State (COS) on selected input pins. This
feature is capable of detecting input Change-of-States
even in Sleep mode, when the clocks are disabled.
Depending on the device pin count, there are up to
22 external signals that may be selected (enabled) for
generating an interrupt request on a Change-of-State.
There are four control registers associated with the CN
module. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source that is connected
to the pin, and eliminate the need for external resistors
when push button or keypad devices are connected.
The pull-ups are enabled separately using the CNPU1
and CNPU2 registers, which contain the control bits for
each of the CN pins. Setting any of the control bits
enables the weak pull-ups for the corresponding pins.
When the internal pull-up is selected, the pin pulls up to
V
DD – 0.7V (typical). Make sure that there is no external
pull-up source when the internal pull-ups are enabled,
as the voltage difference can cause a current path.
EXAMPLE 10-1: PORT WRITE/READ EXAMPLE
Port or Pin
Tolerated
Input
Description
PORTA<4:0> V
DD Only VDD input levels
are tolerated.
PORTB<15:12>
PORTB<4:0>
PORTC<2:0>
(1)
PORTA<10:7>
(1)
5.5V Tolerates input levels
above V
DD, useful for
most standard logic.
PORTB<11:5>
PORTC<9:3>
(1)
Note 1: Unavailable on 28-pin devices.
Note: Pull-ups on Change Notification pins
should always be disabled whenever the
port pin is configured as a digital output.
MOV 0xFF00, W0 ; Configure PORTB<15:8> as inputs
MOV W0, TRISBB ; and PORTB<7:0> as outputs
NOP ; Delay 1 cycle
BTSS PORTB, #13 ; Next Instruction